vsync_period       86 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c 	u32 hsync_period, vsync_period;
vsync_period      100 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c 	vsync_period = p->vsync_pulse_width + p->v_back_porch + p->height +
vsync_period      105 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c 	display_v_end = ((vsync_period - p->v_front_porch) * hsync_period) +
vsync_period      170 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c 	DPU_REG_WRITE(c, INTF_VSYNC_PERIOD_F0, vsync_period * hsync_period);
vsync_period       44 drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c 	uint32_t dsi_hsync_skew, vsync_period, vsync_len, ctrl_pol;
vsync_period       64 drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c 	vsync_period = mode->vtotal * mode->htotal;
vsync_period       67 drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c 	display_v_end = vsync_period - ((mode->vsync_start - mode->vdisplay) * mode->htotal) + dsi_hsync_skew - 1;
vsync_period       72 drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c 	mdp4_write(mdp4_kms, REG_MDP4_DSI_VSYNC_PERIOD, vsync_period);
vsync_period       90 drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c 	uint32_t dtv_hsync_skew, vsync_period, vsync_len, ctrl_pol;
vsync_period      114 drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c 	vsync_period = mode->vtotal * mode->htotal;
vsync_period      117 drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c 	display_v_end = vsync_period - ((mode->vsync_start - mode->vdisplay) * mode->htotal) + dtv_hsync_skew - 1;
vsync_period      122 drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c 	mdp4_write(mdp4_kms, REG_MDP4_DTV_VSYNC_PERIOD, vsync_period);
vsync_period      261 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c 	uint32_t lcdc_hsync_skew, vsync_period, vsync_len, ctrl_pol;
vsync_period      285 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c 	vsync_period = mode->vtotal * mode->htotal;
vsync_period      288 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c 	display_v_end = vsync_period - ((mode->vsync_start - mode->vdisplay) * mode->htotal) + lcdc_hsync_skew - 1;
vsync_period      293 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c 	mdp4_write(mdp4_kms, REG_MDP4_LCDC_VSYNC_PERIOD, vsync_period);
vsync_period      102 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c 	uint32_t dtv_hsync_skew, vsync_period, vsync_len, ctrl_pol;
vsync_period      150 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c 	vsync_period = mode->vtotal * mode->htotal;
vsync_period      153 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c 	display_v_end = vsync_period - ((mode->vsync_start - mode->vdisplay) * mode->htotal) + dtv_hsync_skew - 1;
vsync_period      170 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c 	mdp5_write(mdp5_kms, REG_MDP5_INTF_VSYNC_PERIOD_F0(intf), vsync_period);