vsr 41 arch/powerpc/lib/sstep.c extern void load_vsrn(int vsr, const void *p); vsr 42 arch/powerpc/lib/sstep.c extern void store_vsrn(int vsr, void *p); vsr 439 drivers/gpu/drm/amd/display/dc/calcs/calcs_logger.h DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] vsr[%d]:%d", i, bw_fixed_to_int(data->vsr[i])); vsr 472 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->vsr[i] = bw_mul(data->vsr_after_stereo, bw_int_to_fixed(2)); vsr 475 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->vsr[i] = data->vsr_after_stereo; vsr 526 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c if (bw_neq(data->vsr[i], bw_int_to_fixed(1))) { vsr 527 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c if (bw_mtn(data->vsr[i], bw_int_to_fixed(4))) { vsr 531 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c if (bw_mtn(data->vsr[i], data->v_taps[i])) { vsr 790 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->v_filter_init[i] = bw_floor2(bw_div((bw_add(bw_add(bw_add(bw_int_to_fixed(1), data->v_taps[i]), data->vsr[i]), bw_mul(bw_mul(bw_int_to_fixed(data->interlace_mode[i]), bw_frc_to_fixed(5, 10)), data->vsr[i]))), bw_int_to_fixed(2)), bw_int_to_fixed(1)); vsr 807 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c if ((bw_mtn(data->vsr[i], bw_int_to_fixed(1)) && surface_type[i] == bw_def_graphics) || data->panning_and_bezel_adjustment == bw_def_any_lines) { vsr 810 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c else if ((((dceip->underlay_downscale_prefetch_enabled == 1 && surface_type[i] != bw_def_graphics) || surface_type[i] == bw_def_graphics) && (bw_mtn(data->lb_partitions[i], bw_add(data->v_taps[i], bw_ceil2(data->vsr[i], bw_int_to_fixed(1))))))) { vsr 818 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->lb_lines_in_per_line_out_in_middle_of_frame[i] = bw_max2(bw_int_to_fixed(1), data->vsr[i]); vsr 820 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c else if (bw_leq(data->vsr[i], bw_int_to_fixed(1))) { vsr 822 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c } else if (bw_leq(data->vsr[i], vsr 825 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c } else if (bw_leq(data->vsr[i], vsr 829 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c else if (bw_leq(data->vsr[i], bw_int_to_fixed(2))) { vsr 832 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c else if (bw_leq(data->vsr[i], bw_int_to_fixed(3))) { vsr 1181 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->src_pixels_for_last_output_pixel[i] = bw_mul(data->source_width_rounded_up_to_chunks[i], bw_max2(bw_ceil2(data->v_filter_init[i], bw_int_to_fixed(dceip->lines_interleaved_into_lb)), bw_mul(bw_ceil2(data->vsr[i], bw_int_to_fixed(dceip->lines_interleaved_into_lb)), data->horizontal_blank_and_chunk_granularity_factor[i]))); vsr 1288 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c if (bw_ltn(data->vsr[i], bw_int_to_fixed(2))) { vsr 1289 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->cursor_latency_hiding[i] = bw_div(bw_div(bw_mul((bw_sub(dceip->cursor_dcp_buffer_lines, bw_int_to_fixed(1))), data->h_total[i]), data->vsr[i]), data->pixel_rate[i]); vsr 1292 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->cursor_latency_hiding[i] = bw_div(bw_div(bw_mul((bw_sub(dceip->cursor_dcp_buffer_lines, bw_int_to_fixed(3))), data->h_total[i]), data->vsr[i]), data->pixel_rate[i]); vsr 1302 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c if (dceip->graphics_lb_nodownscaling_multi_line_prefetching == 1 && (bw_equ(data->vsr[i], bw_int_to_fixed(1)) || (bw_leq(data->vsr[i], bw_frc_to_fixed(8, 10)) && bw_leq(data->v_taps[i], bw_int_to_fixed(2)) && data->lb_bpc[i] == 8)) && surface_type[i] == bw_def_graphics) { vsr 1304 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->minimum_latency_hiding[i] = bw_sub(bw_div(bw_mul((bw_div((bw_add(bw_sub(data->lb_partitions[i], bw_int_to_fixed(2)), bw_div(bw_div(data->data_buffer_size[i], bw_int_to_fixed(data->bytes_per_pixel[i])), data->source_width_pixels[i]))), data->vsr[i])), data->h_total[i]), data->pixel_rate[i]), data->total_dmifmc_urgent_latency); vsr 1306 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->minimum_latency_hiding[i] = bw_sub(bw_div(bw_mul((bw_div((bw_add(bw_sub(data->lb_partitions[i], bw_int_to_fixed(1)), bw_div(bw_div(data->data_buffer_size[i], bw_int_to_fixed(data->bytes_per_pixel[i])), data->source_width_pixels[i]))), data->vsr[i])), data->h_total[i]), data->pixel_rate[i]), data->total_dmifmc_urgent_latency); vsr 1309 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->minimum_latency_hiding[i] = bw_sub(bw_div(bw_mul((bw_div((bw_add(bw_int_to_fixed(1 + data->line_buffer_prefetch[i]), bw_div(bw_div(data->data_buffer_size[i], bw_int_to_fixed(data->bytes_per_pixel[i])), data->source_width_pixels[i]))), data->vsr[i])), data->h_total[i]), data->pixel_rate[i]), data->total_dmifmc_urgent_latency); vsr 1443 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c if ((i == j || data->display_synchronization_enabled) && (data->enable[j] == 1 && bw_equ(data->source_width_rounded_up_to_chunks[i], data->source_width_rounded_up_to_chunks[j]) && bw_equ(data->source_height_rounded_up_to_chunks[i], data->source_height_rounded_up_to_chunks[j]) && bw_equ(data->vsr[i], data->vsr[j]) && bw_equ(data->hsr[i], data->hsr[j]) && bw_equ(data->pixel_rate[i], data->pixel_rate[j]))) { vsr 1477 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->average_bandwidth_no_compression[i] = bw_div(bw_mul(bw_mul(bw_div(bw_mul(data->source_width_rounded_up_to_chunks[i], bw_int_to_fixed(data->bytes_per_pixel[i])), (bw_div(data->h_total[i], data->pixel_rate[i]))), data->vsr[i]), data->bytes_per_request[i]), data->useful_bytes_per_request[i]); vsr 1507 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->min_cursor_memory_interface_buffer_size_in_time = bw_min2(data->min_cursor_memory_interface_buffer_size_in_time, bw_div(bw_mul(bw_div(bw_int_to_fixed(num_cursor_lines), data->vsr[i]), data->h_total[i]), data->pixel_rate[i])); vsr 1929 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->stutter_refresh_duration[i] = bw_sub(bw_mul(bw_div(bw_div(bw_mul(bw_div(bw_div(data->adjusted_data_buffer_size[i], bw_int_to_fixed(data->bytes_per_pixel[i])), data->source_width_rounded_up_to_chunks[i]), data->h_total[i]), data->vsr[i]), data->pixel_rate[i]), data->compression_rate[i]), bw_max2(bw_int_to_fixed(0), bw_sub(data->stutter_exit_watermark[i], bw_div(bw_mul((bw_sub(data->lb_partitions[i], bw_int_to_fixed(1))), data->h_total[i]), data->pixel_rate[i])))); vsr 1930 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->stutter_dmif_buffer_size[i] = bw_div(bw_mul(bw_mul(bw_div(bw_mul(bw_mul(data->stutter_refresh_duration[i], bw_int_to_fixed(data->bytes_per_pixel[i])), data->source_width_rounded_up_to_chunks[i]), data->h_total[i]), data->vsr[i]), data->pixel_rate[i]), data->compression_rate[i]); vsr 403 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h struct bw_fixed vsr[maximum_number_of_surfaces]; vsr 184 drivers/regulator/bcm590xx-regulator.c BCM590XX_REG_RANGES(vsr, dcdc_iosr1_ranges),