vready_after_vcount0  215 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 				dlg_regs->chunk_hdl_adjust_cur1, dlg_regs->vready_after_vcount0, dlg_regs->dst_y_delta_drq_limit,
vready_after_vcount0  275 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c 				dlg_regs->chunk_hdl_adjust_cur1, dlg_regs->vready_after_vcount0, dlg_regs->dst_y_delta_drq_limit,
vready_after_vcount0 1029 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 			disp_dlg_regs->vready_after_vcount0 = 1;
vready_after_vcount0 1031 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 			disp_dlg_regs->vready_after_vcount0 = 0;
vready_after_vcount0 1036 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 			disp_dlg_regs->vready_after_vcount0 = 1;
vready_after_vcount0 1038 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 			disp_dlg_regs->vready_after_vcount0 = 0;
vready_after_vcount0 1029 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 			disp_dlg_regs->vready_after_vcount0 = 1;
vready_after_vcount0 1031 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 			disp_dlg_regs->vready_after_vcount0 = 0;
vready_after_vcount0 1036 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 			disp_dlg_regs->vready_after_vcount0 = 1;
vready_after_vcount0 1038 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 			disp_dlg_regs->vready_after_vcount0 = 0;
vready_after_vcount0 1069 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 			disp_dlg_regs->vready_after_vcount0 = 1;
vready_after_vcount0 1071 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 			disp_dlg_regs->vready_after_vcount0 = 0;
vready_after_vcount0 1076 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 			disp_dlg_regs->vready_after_vcount0 = 1;
vready_after_vcount0 1078 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 			disp_dlg_regs->vready_after_vcount0 = 0;
vready_after_vcount0  445 drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h 	unsigned int vready_after_vcount0;
vready_after_vcount0  311 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c 			dlg_regs.vready_after_vcount0);