vqx_misc_int      454 drivers/crypto/cavium/cpt/cptvf_main.c 	union cptx_vqx_misc_int vqx_misc_int;
vqx_misc_int      456 drivers/crypto/cavium/cpt/cptvf_main.c 	vqx_misc_int.u = cpt_read_csr64(cptvf->reg_base,
vqx_misc_int      459 drivers/crypto/cavium/cpt/cptvf_main.c 	vqx_misc_int.s.dovf = 1;
vqx_misc_int      461 drivers/crypto/cavium/cpt/cptvf_main.c 			vqx_misc_int.u);
vqx_misc_int      466 drivers/crypto/cavium/cpt/cptvf_main.c 	union cptx_vqx_misc_int vqx_misc_int;
vqx_misc_int      468 drivers/crypto/cavium/cpt/cptvf_main.c 	vqx_misc_int.u = cpt_read_csr64(cptvf->reg_base,
vqx_misc_int      471 drivers/crypto/cavium/cpt/cptvf_main.c 	vqx_misc_int.s.irde = 1;
vqx_misc_int      473 drivers/crypto/cavium/cpt/cptvf_main.c 			vqx_misc_int.u);
vqx_misc_int      478 drivers/crypto/cavium/cpt/cptvf_main.c 	union cptx_vqx_misc_int vqx_misc_int;
vqx_misc_int      480 drivers/crypto/cavium/cpt/cptvf_main.c 	vqx_misc_int.u = cpt_read_csr64(cptvf->reg_base,
vqx_misc_int      483 drivers/crypto/cavium/cpt/cptvf_main.c 	vqx_misc_int.s.nwrp = 1;
vqx_misc_int      485 drivers/crypto/cavium/cpt/cptvf_main.c 			CPTX_VQX_MISC_INT(0, 0), vqx_misc_int.u);
vqx_misc_int      490 drivers/crypto/cavium/cpt/cptvf_main.c 	union cptx_vqx_misc_int vqx_misc_int;
vqx_misc_int      492 drivers/crypto/cavium/cpt/cptvf_main.c 	vqx_misc_int.u = cpt_read_csr64(cptvf->reg_base,
vqx_misc_int      495 drivers/crypto/cavium/cpt/cptvf_main.c 	vqx_misc_int.s.mbox = 1;
vqx_misc_int      497 drivers/crypto/cavium/cpt/cptvf_main.c 			vqx_misc_int.u);
vqx_misc_int      502 drivers/crypto/cavium/cpt/cptvf_main.c 	union cptx_vqx_misc_int vqx_misc_int;
vqx_misc_int      504 drivers/crypto/cavium/cpt/cptvf_main.c 	vqx_misc_int.u = cpt_read_csr64(cptvf->reg_base,
vqx_misc_int      507 drivers/crypto/cavium/cpt/cptvf_main.c 	vqx_misc_int.s.swerr = 1;
vqx_misc_int      509 drivers/crypto/cavium/cpt/cptvf_main.c 			vqx_misc_int.u);