vpp_hsc_phase_ctrl 535 drivers/gpu/drm/meson/meson_crtc.c writel_relaxed(priv->viu.vpp_hsc_phase_ctrl, vpp_hsc_phase_ctrl 114 drivers/gpu/drm/meson/meson_drv.h uint32_t vpp_hsc_phase_ctrl; vpp_hsc_phase_ctrl 317 drivers/gpu/drm/meson/meson_overlay.c priv->viu.vpp_hsc_phase_ctrl = (1 << 21) | (4 << 16);