vp_width          320 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 		unsigned int vp_width,
vp_width          448 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 		rq_dlg_param->swath_width_ub = dml_round_to_multiple(vp_width - 1, blk256_width, 1)
vp_width          486 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 		meta_row_width_ub = dml_round_to_multiple(vp_width - 1, meta_req_width, 1)
vp_width          617 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 			dpte_row_width_ub = dml_round_to_multiple(vp_width - 1, dpte_req_width, 1)
vp_width          674 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 	unsigned int vp_width = 0;
vp_width          682 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 		vp_width = pipe_src_param.viewport_width_c / ppe;
vp_width          687 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 		vp_width = pipe_src_param.viewport_width / ppe;
vp_width          709 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 			vp_width,
vp_width          320 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 		unsigned int vp_width,
vp_width          448 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 		rq_dlg_param->swath_width_ub = dml_round_to_multiple(vp_width - 1, blk256_width, 1)
vp_width          486 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 		meta_row_width_ub = dml_round_to_multiple(vp_width - 1, meta_req_width, 1)
vp_width          617 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 			dpte_row_width_ub = dml_round_to_multiple(vp_width - 1, dpte_req_width, 1)
vp_width          674 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 	unsigned int vp_width = 0;
vp_width          682 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 		vp_width = pipe_src_param.viewport_width_c / ppe;
vp_width          687 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 		vp_width = pipe_src_param.viewport_width / ppe;
vp_width          709 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 			vp_width,
vp_width          308 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 		unsigned int vp_width,
vp_width          441 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 		rq_dlg_param->swath_width_ub = dml_round_to_multiple(vp_width - 1, blk256_width, 1)
vp_width          481 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 		meta_row_width_ub = dml_round_to_multiple(vp_width - 1, meta_req_width, 1)
vp_width          620 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 			dpte_row_width_ub = dml_round_to_multiple(vp_width - 1, dpte_req_width, 1)
vp_width          684 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 	unsigned int vp_width = 0;
vp_width          692 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 		vp_width = pipe_param.src.viewport_width_c / ppe;
vp_width          697 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 		vp_width = pipe_param.src.viewport_width / ppe;
vp_width          719 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 			vp_width = dml_min(full_src_vp_width, src_hactive_half);
vp_width          720 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 			dml_print("DML_DLG: %s: vp_width = %d\n", __func__, vp_width);
vp_width          750 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 			vp_width,
vp_width          368 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 		unsigned int vp_width,
vp_width          529 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 	if (!surf_vert && vp_width > (2560 + 16) && bytes_per_element >= 4 && log2_vmpg_bytes == 12
vp_width          545 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 	unsigned int vp_width = 0;
vp_width          607 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 		vp_width = pipe_src_param.viewport_width_c / ppe;
vp_width          612 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 		vp_width = pipe_src_param.viewport_width / ppe;
vp_width          676 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 		rq_dlg_param->swath_width_ub = dml_round_to_multiple(vp_width - 1, blk256_width, 1)
vp_width          718 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 		meta_row_width_ub = dml_round_to_multiple(vp_width - 1, meta_req_width, 1)
vp_width          855 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 			dpte_row_width_ub = dml_round_to_multiple(vp_width - 1, dpte_req_width, 1)
vp_width          875 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 	if (!surf_vert && vp_width > (2560 + 16) && bytes_per_element >= 4 && log2_vmpg_bytes == 12
vp_width          913 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 			vp_width,