vouctl            173 drivers/gpu/drm/zte/zx_vou.c 	void __iomem *vouctl;
vouctl            229 drivers/gpu/drm/zte/zx_vou.c 	zx_writel_mask(vou->vouctl + VOU_INF_HDMI_CTRL, VOU_HDMI_AUD_MASK, aud);
vouctl            258 drivers/gpu/drm/zte/zx_vou.c 	zx_writel_mask(vou->vouctl + VOU_INF_DATA_SEL, 0x3 << data_sel_shift,
vouctl            262 drivers/gpu/drm/zte/zx_vou.c 	zx_writel_mask(vou->vouctl + VOU_INF_CH_SEL, 0x1 << id,
vouctl            266 drivers/gpu/drm/zte/zx_vou.c 	zx_writel_mask(vou->vouctl + VOU_CLK_SEL, inf->clocks_sel_bits,
vouctl            270 drivers/gpu/drm/zte/zx_vou.c 	zx_writel_mask(vou->vouctl + VOU_CLK_EN, inf->clocks_en_bits,
vouctl            274 drivers/gpu/drm/zte/zx_vou.c 	zx_writel_mask(vou->vouctl + VOU_INF_EN, 1 << id, 1 << id);
vouctl            283 drivers/gpu/drm/zte/zx_vou.c 	zx_writel_mask(vou->vouctl + VOU_INF_EN, 1 << id, 0);
vouctl            286 drivers/gpu/drm/zte/zx_vou.c 	zx_writel_mask(vou->vouctl + VOU_CLK_EN, inf->clocks_en_bits, 0);
vouctl            298 drivers/gpu/drm/zte/zx_vou.c 	zx_writel_mask(vou->vouctl + VOU_DIV_PARA, DIV_PARA_UPDATE, 0);
vouctl            338 drivers/gpu/drm/zte/zx_vou.c 		zx_writel_mask(vou->vouctl + reg, 0x7 << shift,
vouctl            343 drivers/gpu/drm/zte/zx_vou.c 	zx_writel_mask(vou->vouctl + VOU_DIV_PARA, DIV_PARA_UPDATE,
vouctl            618 drivers/gpu/drm/zte/zx_vou.c 		zx_writel_mask(vou->vouctl + VOU_CLK_SEL, bits->clksel, 0);
vouctl            622 drivers/gpu/drm/zte/zx_vou.c 		zx_writel_mask(vou->vouctl + VOU_CLK_SEL, bits->clksel,
vouctl            737 drivers/gpu/drm/zte/zx_vou.c 	zx_writel(vou->vouctl + VOU_SOFT_RST, ~0);
vouctl            740 drivers/gpu/drm/zte/zx_vou.c 	zx_writel(vou->vouctl + VOU_CLK_EN, ~0);
vouctl            801 drivers/gpu/drm/zte/zx_vou.c 	vou->vouctl = devm_ioremap_resource(dev, res);
vouctl            802 drivers/gpu/drm/zte/zx_vou.c 	if (IS_ERR(vou->vouctl)) {
vouctl            803 drivers/gpu/drm/zte/zx_vou.c 		ret = PTR_ERR(vou->vouctl);