vou 123 drivers/gpu/drm/zte/zx_vou.c struct zx_vou_hw *vou; vou 220 drivers/gpu/drm/zte/zx_vou.c return zcrtc->vou; vou 227 drivers/gpu/drm/zte/zx_vou.c struct zx_vou_hw *vou = zcrtc->vou; vou 229 drivers/gpu/drm/zte/zx_vou.c zx_writel_mask(vou->vouctl + VOU_INF_HDMI_CTRL, VOU_HDMI_AUD_MASK, aud); vou 235 drivers/gpu/drm/zte/zx_vou.c struct zx_vou_hw *vou = zcrtc->vou; vou 258 drivers/gpu/drm/zte/zx_vou.c zx_writel_mask(vou->vouctl + VOU_INF_DATA_SEL, 0x3 << data_sel_shift, vou 262 drivers/gpu/drm/zte/zx_vou.c zx_writel_mask(vou->vouctl + VOU_INF_CH_SEL, 0x1 << id, vou 266 drivers/gpu/drm/zte/zx_vou.c zx_writel_mask(vou->vouctl + VOU_CLK_SEL, inf->clocks_sel_bits, vou 270 drivers/gpu/drm/zte/zx_vou.c zx_writel_mask(vou->vouctl + VOU_CLK_EN, inf->clocks_en_bits, vou 274 drivers/gpu/drm/zte/zx_vou.c zx_writel_mask(vou->vouctl + VOU_INF_EN, 1 << id, 1 << id); vou 279 drivers/gpu/drm/zte/zx_vou.c struct zx_vou_hw *vou = crtc_to_vou(crtc); vou 283 drivers/gpu/drm/zte/zx_vou.c zx_writel_mask(vou->vouctl + VOU_INF_EN, 1 << id, 0); vou 286 drivers/gpu/drm/zte/zx_vou.c zx_writel_mask(vou->vouctl + VOU_CLK_EN, inf->clocks_en_bits, 0); vou 293 drivers/gpu/drm/zte/zx_vou.c struct zx_vou_hw *vou = zcrtc->vou; vou 298 drivers/gpu/drm/zte/zx_vou.c zx_writel_mask(vou->vouctl + VOU_DIV_PARA, DIV_PARA_UPDATE, 0); vou 338 drivers/gpu/drm/zte/zx_vou.c zx_writel_mask(vou->vouctl + reg, 0x7 << shift, vou 343 drivers/gpu/drm/zte/zx_vou.c zx_writel_mask(vou->vouctl + VOU_DIV_PARA, DIV_PARA_UPDATE, vou 358 drivers/gpu/drm/zte/zx_vou.c struct zx_vou_hw *vou = zcrtc->vou; vou 372 drivers/gpu/drm/zte/zx_vou.c zx_writel(vou->timing + regs->fir_active, val); vou 377 drivers/gpu/drm/zte/zx_vou.c zx_writel(vou->timing + regs->fir_htiming, val); vou 382 drivers/gpu/drm/zte/zx_vou.c zx_writel(vou->timing + regs->fir_vtiming, val); vou 388 drivers/gpu/drm/zte/zx_vou.c val = zx_readl(vou->timing + SEC_V_ACTIVE); vou 391 drivers/gpu/drm/zte/zx_vou.c zx_writel(vou->timing + SEC_V_ACTIVE, val); vou 400 drivers/gpu/drm/zte/zx_vou.c zx_writel(vou->timing + regs->sec_vtiming, val); vou 409 drivers/gpu/drm/zte/zx_vou.c zx_writel_mask(vou->timing + TIMING_CTRL, bits->polarity_mask, vou 416 drivers/gpu/drm/zte/zx_vou.c zx_writel(vou->timing + regs->timing_shift, val); vou 417 drivers/gpu/drm/zte/zx_vou.c zx_writel(vou->timing + regs->timing_pi_shift, H_PI_SHIFT_VAL); vou 421 drivers/gpu/drm/zte/zx_vou.c zx_writel_mask(vou->timing + SCAN_CTRL, scan_mask, vou 425 drivers/gpu/drm/zte/zx_vou.c zx_writel_mask(vou->timing + TIMING_TC_ENABLE, bits->tc_enable, vou 448 drivers/gpu/drm/zte/zx_vou.c DRM_DEV_ERROR(vou->dev, "failed to set pixclk rate: %d\n", ret); vou 454 drivers/gpu/drm/zte/zx_vou.c DRM_DEV_ERROR(vou->dev, "failed to enable pixclk: %d\n", ret); vou 462 drivers/gpu/drm/zte/zx_vou.c struct zx_vou_hw *vou = zcrtc->vou; vou 472 drivers/gpu/drm/zte/zx_vou.c zx_writel_mask(vou->timing + TIMING_TC_ENABLE, bits->tc_enable, 0); vou 502 drivers/gpu/drm/zte/zx_vou.c struct zx_vou_hw *vou = crtc_to_vou(crtc); vou 505 drivers/gpu/drm/zte/zx_vou.c zx_writel_mask(vou->timing + TIMING_INT_CTRL, int_frame_mask, vou 514 drivers/gpu/drm/zte/zx_vou.c struct zx_vou_hw *vou = crtc_to_vou(crtc); vou 516 drivers/gpu/drm/zte/zx_vou.c zx_writel_mask(vou->timing + TIMING_INT_CTRL, vou 531 drivers/gpu/drm/zte/zx_vou.c static int zx_crtc_init(struct drm_device *drm, struct zx_vou_hw *vou, vou 534 drivers/gpu/drm/zte/zx_vou.c struct device *dev = vou->dev; vou 543 drivers/gpu/drm/zte/zx_vou.c zcrtc->vou = vou; vou 553 drivers/gpu/drm/zte/zx_vou.c zplane->layer = vou->osd + MAIN_GL_OFFSET; vou 554 drivers/gpu/drm/zte/zx_vou.c zplane->csc = vou->osd + MAIN_GL_CSC_OFFSET; vou 555 drivers/gpu/drm/zte/zx_vou.c zplane->hbsc = vou->osd + MAIN_HBSC_OFFSET; vou 556 drivers/gpu/drm/zte/zx_vou.c zplane->rsz = vou->otfppu + MAIN_RSZ_OFFSET; vou 558 drivers/gpu/drm/zte/zx_vou.c zcrtc->chnreg = vou->osd + OSD_MAIN_CHN; vou 559 drivers/gpu/drm/zte/zx_vou.c zcrtc->chncsc = vou->osd + MAIN_CHN_CSC_OFFSET; vou 560 drivers/gpu/drm/zte/zx_vou.c zcrtc->dither = vou->osd + MAIN_DITHER_OFFSET; vou 564 drivers/gpu/drm/zte/zx_vou.c zplane->layer = vou->osd + AUX_GL_OFFSET; vou 565 drivers/gpu/drm/zte/zx_vou.c zplane->csc = vou->osd + AUX_GL_CSC_OFFSET; vou 566 drivers/gpu/drm/zte/zx_vou.c zplane->hbsc = vou->osd + AUX_HBSC_OFFSET; vou 567 drivers/gpu/drm/zte/zx_vou.c zplane->rsz = vou->otfppu + AUX_RSZ_OFFSET; vou 569 drivers/gpu/drm/zte/zx_vou.c zcrtc->chnreg = vou->osd + OSD_AUX_CHN; vou 570 drivers/gpu/drm/zte/zx_vou.c zcrtc->chncsc = vou->osd + AUX_CHN_CSC_OFFSET; vou 571 drivers/gpu/drm/zte/zx_vou.c zcrtc->dither = vou->osd + AUX_DITHER_OFFSET; vou 602 drivers/gpu/drm/zte/zx_vou.c vou->main_crtc = zcrtc; vou 604 drivers/gpu/drm/zte/zx_vou.c vou->aux_crtc = zcrtc; vou 612 drivers/gpu/drm/zte/zx_vou.c struct zx_vou_hw *vou = zcrtc->vou; vou 617 drivers/gpu/drm/zte/zx_vou.c zx_writel_mask(vou->osd + OSD_CTRL0, bits->chnsel, 0); vou 618 drivers/gpu/drm/zte/zx_vou.c zx_writel_mask(vou->vouctl + VOU_CLK_SEL, bits->clksel, 0); vou 620 drivers/gpu/drm/zte/zx_vou.c zx_writel_mask(vou->osd + OSD_CTRL0, bits->chnsel, vou 622 drivers/gpu/drm/zte/zx_vou.c zx_writel_mask(vou->vouctl + VOU_CLK_SEL, bits->clksel, vou 626 drivers/gpu/drm/zte/zx_vou.c zx_writel_mask(vou->osd + OSD_CTRL0, bits->enable, bits->enable); vou 633 drivers/gpu/drm/zte/zx_vou.c struct zx_vou_hw *vou = zcrtc->vou; vou 637 drivers/gpu/drm/zte/zx_vou.c zx_writel_mask(vou->osd + OSD_CTRL0, bits->enable, 0); vou 640 drivers/gpu/drm/zte/zx_vou.c static void zx_overlay_init(struct drm_device *drm, struct zx_vou_hw *vou) vou 642 drivers/gpu/drm/zte/zx_vou.c struct device *dev = vou->dev; vou 658 drivers/gpu/drm/zte/zx_vou.c zplane->layer = vou->osd + OSD_VL_OFFSET(i); vou 659 drivers/gpu/drm/zte/zx_vou.c zplane->hbsc = vou->osd + HBSC_VL_OFFSET(i); vou 660 drivers/gpu/drm/zte/zx_vou.c zplane->rsz = vou->otfppu + RSZ_VL_OFFSET(i); vou 684 drivers/gpu/drm/zte/zx_vou.c struct zx_vou_hw *vou = dev_id; vou 688 drivers/gpu/drm/zte/zx_vou.c state = zx_readl(vou->timing + TIMING_INT_STATE); vou 689 drivers/gpu/drm/zte/zx_vou.c zx_writel(vou->timing + TIMING_INT_STATE, state); vou 692 drivers/gpu/drm/zte/zx_vou.c drm_crtc_handle_vblank(&vou->main_crtc->crtc); vou 695 drivers/gpu/drm/zte/zx_vou.c drm_crtc_handle_vblank(&vou->aux_crtc->crtc); vou 698 drivers/gpu/drm/zte/zx_vou.c state = zx_readl(vou->osd + OSD_INT_STA); vou 699 drivers/gpu/drm/zte/zx_vou.c zx_writel(vou->osd + OSD_INT_CLRSTA, state); vou 702 drivers/gpu/drm/zte/zx_vou.c zx_osd_int_update(vou->main_crtc); vou 705 drivers/gpu/drm/zte/zx_vou.c zx_osd_int_update(vou->aux_crtc); vou 708 drivers/gpu/drm/zte/zx_vou.c DRM_DEV_ERROR(vou->dev, "OSD ERROR: 0x%08x!\n", state); vou 713 drivers/gpu/drm/zte/zx_vou.c static void vou_dtrc_init(struct zx_vou_hw *vou) vou 716 drivers/gpu/drm/zte/zx_vou.c zx_writel_mask(vou->dtrc + DTRC_DETILE_CTRL, vou 720 drivers/gpu/drm/zte/zx_vou.c zx_writel_mask(vou->dtrc + DTRC_DETILE_CTRL, DETILE_ARIDR_MODE_MASK, vou 724 drivers/gpu/drm/zte/zx_vou.c zx_writel_mask(vou->dtrc + DTRC_F0_CTRL, DTRC_DECOMPRESS_BYPASS, vou 726 drivers/gpu/drm/zte/zx_vou.c zx_writel_mask(vou->dtrc + DTRC_F1_CTRL, DTRC_DECOMPRESS_BYPASS, vou 730 drivers/gpu/drm/zte/zx_vou.c zx_writel(vou->dtrc + DTRC_ARID, DTRC_ARID3(0xf) | DTRC_ARID2(0xe) | vou 734 drivers/gpu/drm/zte/zx_vou.c static void vou_hw_init(struct zx_vou_hw *vou) vou 737 drivers/gpu/drm/zte/zx_vou.c zx_writel(vou->vouctl + VOU_SOFT_RST, ~0); vou 740 drivers/gpu/drm/zte/zx_vou.c zx_writel(vou->vouctl + VOU_CLK_EN, ~0); vou 743 drivers/gpu/drm/zte/zx_vou.c zx_writel(vou->osd + OSD_INT_CLRSTA, ~0); vou 744 drivers/gpu/drm/zte/zx_vou.c zx_writel(vou->timing + TIMING_INT_STATE, ~0); vou 747 drivers/gpu/drm/zte/zx_vou.c zx_writel(vou->osd + OSD_INT_MSK, OSD_INT_ENABLE); vou 748 drivers/gpu/drm/zte/zx_vou.c zx_writel(vou->timing + TIMING_INT_CTRL, TIMING_INT_ENABLE); vou 751 drivers/gpu/drm/zte/zx_vou.c zx_writel(vou->otfppu + OTFPPU_RSZ_DATA_SOURCE, 0x2a); vou 757 drivers/gpu/drm/zte/zx_vou.c zx_writel_mask(vou->osd + OSD_RST_CLR, RST_PER_FRAME, RST_PER_FRAME); vou 759 drivers/gpu/drm/zte/zx_vou.c vou_dtrc_init(vou); vou 766 drivers/gpu/drm/zte/zx_vou.c struct zx_vou_hw *vou; vou 771 drivers/gpu/drm/zte/zx_vou.c vou = devm_kzalloc(dev, sizeof(*vou), GFP_KERNEL); vou 772 drivers/gpu/drm/zte/zx_vou.c if (!vou) vou 776 drivers/gpu/drm/zte/zx_vou.c vou->osd = devm_ioremap_resource(dev, res); vou 777 drivers/gpu/drm/zte/zx_vou.c if (IS_ERR(vou->osd)) { vou 778 drivers/gpu/drm/zte/zx_vou.c ret = PTR_ERR(vou->osd); vou 784 drivers/gpu/drm/zte/zx_vou.c vou->timing = devm_ioremap_resource(dev, res); vou 785 drivers/gpu/drm/zte/zx_vou.c if (IS_ERR(vou->timing)) { vou 786 drivers/gpu/drm/zte/zx_vou.c ret = PTR_ERR(vou->timing); vou 793 drivers/gpu/drm/zte/zx_vou.c vou->dtrc = devm_ioremap_resource(dev, res); vou 794 drivers/gpu/drm/zte/zx_vou.c if (IS_ERR(vou->dtrc)) { vou 795 drivers/gpu/drm/zte/zx_vou.c ret = PTR_ERR(vou->dtrc); vou 801 drivers/gpu/drm/zte/zx_vou.c vou->vouctl = devm_ioremap_resource(dev, res); vou 802 drivers/gpu/drm/zte/zx_vou.c if (IS_ERR(vou->vouctl)) { vou 803 drivers/gpu/drm/zte/zx_vou.c ret = PTR_ERR(vou->vouctl); vou 810 drivers/gpu/drm/zte/zx_vou.c vou->otfppu = devm_ioremap_resource(dev, res); vou 811 drivers/gpu/drm/zte/zx_vou.c if (IS_ERR(vou->otfppu)) { vou 812 drivers/gpu/drm/zte/zx_vou.c ret = PTR_ERR(vou->otfppu); vou 821 drivers/gpu/drm/zte/zx_vou.c vou->axi_clk = devm_clk_get(dev, "aclk"); vou 822 drivers/gpu/drm/zte/zx_vou.c if (IS_ERR(vou->axi_clk)) { vou 823 drivers/gpu/drm/zte/zx_vou.c ret = PTR_ERR(vou->axi_clk); vou 828 drivers/gpu/drm/zte/zx_vou.c vou->ppu_clk = devm_clk_get(dev, "ppu_wclk"); vou 829 drivers/gpu/drm/zte/zx_vou.c if (IS_ERR(vou->ppu_clk)) { vou 830 drivers/gpu/drm/zte/zx_vou.c ret = PTR_ERR(vou->ppu_clk); vou 835 drivers/gpu/drm/zte/zx_vou.c ret = clk_prepare_enable(vou->axi_clk); vou 841 drivers/gpu/drm/zte/zx_vou.c clk_prepare_enable(vou->ppu_clk); vou 847 drivers/gpu/drm/zte/zx_vou.c vou->dev = dev; vou 848 drivers/gpu/drm/zte/zx_vou.c dev_set_drvdata(dev, vou); vou 850 drivers/gpu/drm/zte/zx_vou.c vou_hw_init(vou); vou 852 drivers/gpu/drm/zte/zx_vou.c ret = devm_request_irq(dev, irq, vou_irq_handler, 0, "zx_vou", vou); vou 858 drivers/gpu/drm/zte/zx_vou.c ret = zx_crtc_init(drm, vou, VOU_CHN_MAIN); vou 865 drivers/gpu/drm/zte/zx_vou.c ret = zx_crtc_init(drm, vou, VOU_CHN_AUX); vou 872 drivers/gpu/drm/zte/zx_vou.c zx_overlay_init(drm, vou); vou 877 drivers/gpu/drm/zte/zx_vou.c clk_disable_unprepare(vou->ppu_clk); vou 879 drivers/gpu/drm/zte/zx_vou.c clk_disable_unprepare(vou->axi_clk); vou 886 drivers/gpu/drm/zte/zx_vou.c struct zx_vou_hw *vou = dev_get_drvdata(dev); vou 888 drivers/gpu/drm/zte/zx_vou.c clk_disable_unprepare(vou->axi_clk); vou 889 drivers/gpu/drm/zte/zx_vou.c clk_disable_unprepare(vou->ppu_clk);