vol_table         203 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c int phm_trim_voltage_table(struct pp_atomctrl_voltage_table *vol_table)
vol_table         210 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c 	PP_ASSERT_WITH_CODE((NULL != vol_table),
vol_table         219 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c 	table->mask_low = vol_table->mask_low;
vol_table         220 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c 	table->phase_delay = vol_table->phase_delay;
vol_table         222 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c 	for (i = 0; i < vol_table->count; i++) {
vol_table         223 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c 		vvalue = vol_table->entries[i].value;
vol_table         236 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c 					vol_table->entries[i].smio_low;
vol_table         241 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c 	memcpy(vol_table, table, sizeof(struct pp_atomctrl_voltage_table));
vol_table         247 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c int phm_get_svi2_mvdd_voltage_table(struct pp_atomctrl_voltage_table *vol_table,
vol_table         256 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c 	PP_ASSERT_WITH_CODE((NULL != vol_table),
vol_table         259 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c 	vol_table->mask_low = 0;
vol_table         260 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c 	vol_table->phase_delay = 0;
vol_table         261 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c 	vol_table->count = dep_table->count;
vol_table         264 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c 		vol_table->entries[i].value = dep_table->entries[i].mvdd;
vol_table         265 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c 		vol_table->entries[i].smio_low = 0;
vol_table         268 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c 	result = phm_trim_voltage_table(vol_table);
vol_table         275 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c int phm_get_svi2_vddci_voltage_table(struct pp_atomctrl_voltage_table *vol_table,
vol_table         284 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c 	PP_ASSERT_WITH_CODE((NULL != vol_table),
vol_table         287 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c 	vol_table->mask_low = 0;
vol_table         288 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c 	vol_table->phase_delay = 0;
vol_table         289 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c 	vol_table->count = dep_table->count;
vol_table         292 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c 		vol_table->entries[i].value = dep_table->entries[i].vddci;
vol_table         293 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c 		vol_table->entries[i].smio_low = 0;
vol_table         296 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c 	result = phm_trim_voltage_table(vol_table);
vol_table         303 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c int phm_get_svi2_vdd_voltage_table(struct pp_atomctrl_voltage_table *vol_table,
vol_table         311 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c 	PP_ASSERT_WITH_CODE((NULL != vol_table),
vol_table         314 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c 	vol_table->mask_low = 0;
vol_table         315 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c 	vol_table->phase_delay = 0;
vol_table         317 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c 	vol_table->count = lookup_table->count;
vol_table         319 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c 	for (i = 0; i < vol_table->count; i++) {
vol_table         320 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c 		vol_table->entries[i].value = lookup_table->entries[i].us_vdd;
vol_table         321 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c 		vol_table->entries[i].smio_low = 0;
vol_table         328 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c 				struct pp_atomctrl_voltage_table *vol_table)
vol_table         332 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c 	if (vol_table->count <= max_vol_steps)
vol_table         335 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c 	diff = vol_table->count - max_vol_steps;
vol_table         338 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c 		vol_table->entries[i] = vol_table->entries[i + diff];
vol_table         340 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c 	vol_table->count = max_vol_steps;
vol_table          75 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h extern int phm_trim_voltage_table(struct pp_atomctrl_voltage_table *vol_table);
vol_table          76 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h extern int phm_get_svi2_mvdd_voltage_table(struct pp_atomctrl_voltage_table *vol_table, phm_ppt_v1_clock_voltage_dependency_table *dep_table);
vol_table          77 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h extern int phm_get_svi2_vddci_voltage_table(struct pp_atomctrl_voltage_table *vol_table, phm_ppt_v1_clock_voltage_dependency_table *dep_table);
vol_table          78 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h extern int phm_get_svi2_vdd_voltage_table(struct pp_atomctrl_voltage_table *vol_table, phm_ppt_v1_voltage_lookup_table *lookup_table);
vol_table          79 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h extern void phm_trim_voltage_table_to_fit_state_table(uint32_t max_vol_steps, struct pp_atomctrl_voltage_table *vol_table);
vol_table         824 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct pp_atomfwctrl_voltage_table vol_table;
vol_table         850 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 				&vol_table)) {
vol_table         851 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			config_telemetry = ((vol_table.telemetry_slope << 8) & 0xff00) |
vol_table         852 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 					(vol_table.telemetry_offset & 0xff);
vol_table         868 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 				&vol_table)) {
vol_table         870 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 					((vol_table.telemetry_slope << 24) & 0xff000000) |
vol_table         871 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 					((vol_table.telemetry_offset << 16) & 0xff0000);
vol_table        1006 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		struct pp_atomfwctrl_voltage_table *vol_table)
vol_table        1013 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	PP_ASSERT_WITH_CODE(vol_table,
vol_table        1021 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	table->mask_low = vol_table->mask_low;
vol_table        1022 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	table->phase_delay = vol_table->phase_delay;
vol_table        1024 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	for (i = 0; i < vol_table->count; i++) {
vol_table        1025 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		vvalue = vol_table->entries[i].value;
vol_table        1038 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 					vol_table->entries[i].smio_low;
vol_table        1043 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	memcpy(vol_table, table, sizeof(struct pp_atomfwctrl_voltage_table));
vol_table        1051 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		struct pp_atomfwctrl_voltage_table *vol_table)
vol_table        1059 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	vol_table->mask_low = 0;
vol_table        1060 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	vol_table->phase_delay = 0;
vol_table        1061 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	vol_table->count = dep_table->count;
vol_table        1063 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	for (i = 0; i < vol_table->count; i++) {
vol_table        1064 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		vol_table->entries[i].value = dep_table->entries[i].mvdd;
vol_table        1065 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		vol_table->entries[i].smio_low = 0;
vol_table        1069 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			vol_table),
vol_table        1078 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		struct pp_atomfwctrl_voltage_table *vol_table)
vol_table        1086 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	vol_table->mask_low = 0;
vol_table        1087 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	vol_table->phase_delay = 0;
vol_table        1088 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	vol_table->count = dep_table->count;
vol_table        1091 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		vol_table->entries[i].value = dep_table->entries[i].vddci;
vol_table        1092 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		vol_table->entries[i].smio_low = 0;
vol_table        1095 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	PP_ASSERT_WITH_CODE(!vega10_trim_voltage_table(hwmgr, vol_table),
vol_table        1104 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		struct pp_atomfwctrl_voltage_table *vol_table)
vol_table        1112 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	vol_table->mask_low = 0;
vol_table        1113 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	vol_table->phase_delay = 0;
vol_table        1114 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	vol_table->count = dep_table->count;
vol_table        1116 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	for (i = 0; i < vol_table->count; i++) {
vol_table        1117 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		vol_table->entries[i].value = dep_table->entries[i].vddc;
vol_table        1118 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		vol_table->entries[i].smio_low = 0;
vol_table        1132 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		struct pp_atomfwctrl_voltage_table *vol_table)
vol_table        1136 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	if (vol_table->count <= max_vol_steps)
vol_table        1139 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	diff = vol_table->count - max_vol_steps;
vol_table        1142 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		vol_table->entries[i] = vol_table->entries[i + diff];
vol_table        1144 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	vol_table->count = max_vol_steps;