VI0_CLK          1069 drivers/pinctrl/sh-pfc/pfc-r8a77470.c 	PINMUX_IPSR_GPSR(IP16_7_4, VI0_CLK),
VI0_CLK          1038 drivers/pinctrl/sh-pfc/pfc-r8a7778.c 	PINMUX_IPSR_GPSR(IP7_21,	VI0_CLK),
VI0_CLK          1691 drivers/pinctrl/sh-pfc/pfc-r8a7778.c VIN_PFC_CLK(vin0_clk,		VI0_CLK);
VI0_CLK          1157 drivers/pinctrl/sh-pfc/pfc-r8a7779.c 	PINMUX_IPSR_GPSR(IP8_20, VI0_CLK),
VI0_CLK          1222 drivers/pinctrl/sh-pfc/pfc-r8a7790.c 	PINMUX_IPSR_MSEL(IP7_28_27, VI0_CLK, SEL_VI0_0),
VI0_CLK           795 drivers/pinctrl/sh-pfc/pfc-r8a7791.c 	PINMUX_SINGLE(VI0_CLK),
VI0_CLK           401 drivers/pinctrl/sh-pfc/pfc-r8a7792.c 	PINMUX_SINGLE(VI0_CLK),
VI0_CLK           996 drivers/pinctrl/sh-pfc/pfc-r8a7794.c 	PINMUX_IPSR_GPSR(IP6_8, VI0_CLK),
VI0_CLK           105 drivers/pinctrl/sh-pfc/pfc-r8a77970.c #define GPSR2_0		F_(VI0_CLK,		IP2_31_28)
VI0_CLK           176 drivers/pinctrl/sh-pfc/pfc-r8a77970.c #define IP2_31_28	FM(VI0_CLK)			FM(MSIOF2_SCK)		FM(SCK3)	F_(0, 0)	FM(HSCK3)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
VI0_CLK           475 drivers/pinctrl/sh-pfc/pfc-r8a77970.c 	PINMUX_IPSR_GPSR(IP2_31_28,	VI0_CLK),
VI0_CLK           119 drivers/pinctrl/sh-pfc/pfc-r8a77980.c #define GPSR2_0		F_(VI0_CLK,		IP2_31_28)
VI0_CLK           209 drivers/pinctrl/sh-pfc/pfc-r8a77980.c #define IP2_31_28	FM(VI0_CLK)			FM(MSIOF2_SCK)		FM(SCK3)		F_(0, 0)	FM(HSCK3)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
VI0_CLK           559 drivers/pinctrl/sh-pfc/pfc-r8a77980.c 	PINMUX_IPSR_GPSR(IP2_31_28,	VI0_CLK),
VI0_CLK          1299 drivers/pinctrl/sh-pfc/pfc-sh7734.c 	PINMUX_IPSR_GPSR(IP11_6_4, VI0_CLK),
VI0_CLK          1629 drivers/pinctrl/sh-pfc/pfc-sh7734.c 	GPIO_FN(SCIF_CLK_A), GPIO_FN(HSPI_CLK_A), GPIO_FN(VI0_CLK),