vm_info_1        1653 arch/ia64/include/asm/pal.h ia64_pal_vm_summary (pal_vm_info_1_u_t *vm_info_1, pal_vm_info_2_u_t *vm_info_2)
vm_info_1        1657 arch/ia64/include/asm/pal.h 	if (vm_info_1)
vm_info_1        1658 arch/ia64/include/asm/pal.h 		vm_info_1->pvi1_val = iprv.v0;
vm_info_1         294 arch/ia64/kernel/palinfo.c 	pal_vm_info_1_u_t vm_info_1;
vm_info_1         302 arch/ia64/kernel/palinfo.c 	if ((status = ia64_pal_vm_summary(&vm_info_1, &vm_info_2)) !=0) {
vm_info_1         314 arch/ia64/kernel/palinfo.c 		     vm_info_1.pal_vm_info_1_s.phys_add_size,
vm_info_1         316 arch/ia64/kernel/palinfo.c 		     vm_info_1.pal_vm_info_1_s.max_pkr+1,
vm_info_1         317 arch/ia64/kernel/palinfo.c 		     vm_info_1.pal_vm_info_1_s.key_size,
vm_info_1         318 arch/ia64/kernel/palinfo.c 		     vm_info_1.pal_vm_info_1_s.hash_tag_id,
vm_info_1         349 arch/ia64/kernel/palinfo.c 			   vm_info_1.pal_vm_info_1_s.vw ? "" : "not ",
vm_info_1         350 arch/ia64/kernel/palinfo.c 			   vm_info_1.pal_vm_info_1_s.max_dtr_entry+1,
vm_info_1         351 arch/ia64/kernel/palinfo.c 			   vm_info_1.pal_vm_info_1_s.max_itr_entry+1);
vm_info_1         375 arch/ia64/kernel/palinfo.c 		     vm_info_1.pal_vm_info_1_s.num_tc_levels,
vm_info_1         376 arch/ia64/kernel/palinfo.c 		     vm_info_1.pal_vm_info_1_s.max_unique_tcs);
vm_info_1         378 arch/ia64/kernel/palinfo.c 		for(i=0; i < vm_info_1.pal_vm_info_1_s.num_tc_levels; i++) {
vm_info_1         716 arch/ia64/kernel/palinfo.c 	pal_vm_info_1_u_t vm_info_1;
vm_info_1         752 arch/ia64/kernel/palinfo.c 	if ((status = ia64_pal_vm_summary(&vm_info_1, &vm_info_2)) !=0) {
vm_info_1         756 arch/ia64/kernel/palinfo.c 	max[0] = vm_info_1.pal_vm_info_1_s.max_itr_entry+1;
vm_info_1         757 arch/ia64/kernel/palinfo.c 	max[1] = vm_info_1.pal_vm_info_1_s.max_dtr_entry+1;
vm_info_1         375 arch/ia64/mm/tlb.c 	pal_vm_info_1_u_t vm_info_1;
vm_info_1         394 arch/ia64/mm/tlb.c 	status = ia64_pal_vm_summary(&vm_info_1, &vm_info_2);
vm_info_1         401 arch/ia64/mm/tlb.c 	per_cpu(ia64_tr_num, cpu) = vm_info_1.pal_vm_info_1_s.max_itr_entry+1;
vm_info_1         403 arch/ia64/mm/tlb.c 				(vm_info_1.pal_vm_info_1_s.max_dtr_entry+1))
vm_info_1         405 arch/ia64/mm/tlb.c 				vm_info_1.pal_vm_info_1_s.max_dtr_entry+1;