vm0               778 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		const struct vm_context0_param *vm0)
vm0               783 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 			VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, vm0->pte_base.high_part);
vm0               785 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 			VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, vm0->pte_base.low_part);
vm0               789 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 			VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, vm0->pte_start.high_part);
vm0               791 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 			VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, vm0->pte_start.low_part);
vm0               795 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 			VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, vm0->pte_end.high_part);
vm0               797 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 			VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, vm0->pte_end.low_part);
vm0               801 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 			VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, vm0->fault_default.high_part,
vm0               804 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 			VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, vm0->fault_default.low_part);
vm0              1768 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		struct vm_context0_param *vm0,
vm0              1780 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			PAGE_DIRECTORY_ENTRY_HI32, &vm0->pte_base.high_part);
vm0              1782 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			PAGE_DIRECTORY_ENTRY_LO32, &vm0->pte_base.low_part);
vm0              1785 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			LOGICAL_PAGE_NUMBER_HI4, &vm0->pte_start.high_part);
vm0              1787 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			LOGICAL_PAGE_NUMBER_LO32, &vm0->pte_start.low_part);
vm0              1790 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			LOGICAL_PAGE_NUMBER_HI4, &vm0->pte_end.high_part);
vm0              1792 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			LOGICAL_PAGE_NUMBER_LO32, &vm0->pte_end.low_part);
vm0              1795 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			PHYSICAL_PAGE_ADDR_HI4, &vm0->fault_default.high_part);
vm0              1797 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			PHYSICAL_PAGE_ADDR_LO32, &vm0->fault_default.low_part);
vm0              1807 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	vm0->pte_base.quad_part += fb_base.quad_part;
vm0              1808 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	vm0->pte_base.quad_part -= fb_offset.quad_part;
vm0              1816 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	struct vm_context0_param vm0 = { { { 0 } } };
vm0              1819 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	mmhub_read_vm_context0_settings(hubp1, &vm0, hws);
vm0              1822 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	hubp->funcs->hubp_set_vm_context0_settings(hubp, &vm0);
vm0               106 drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h 			const struct vm_context0_param *vm0);
vm0               150 drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h 			const struct vm_context0_param *vm0);