vlv              1059 drivers/gpu/drm/i915/display/intel_display_power.c 	int pw_idx = power_well->desc->vlv.idx;
vlv              1107 drivers/gpu/drm/i915/display/intel_display_power.c 	int pw_idx = power_well->desc->vlv.idx;
vlv              2791 drivers/gpu/drm/i915/display/intel_display_power.c 			.vlv.idx = PUNIT_PWGT_IDX_DISP2D,
vlv              2803 drivers/gpu/drm/i915/display/intel_display_power.c 			.vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_B_LANES_01,
vlv              2815 drivers/gpu/drm/i915/display/intel_display_power.c 			.vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_B_LANES_23,
vlv              2827 drivers/gpu/drm/i915/display/intel_display_power.c 			.vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_C_LANES_01,
vlv              2839 drivers/gpu/drm/i915/display/intel_display_power.c 			.vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_C_LANES_23,
vlv              2848 drivers/gpu/drm/i915/display/intel_display_power.c 			.vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_BC,
vlv              2878 drivers/gpu/drm/i915/display/intel_display_power.c 			.vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_BC,
vlv              2887 drivers/gpu/drm/i915/display/intel_display_power.c 			.vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_D,
vlv               177 drivers/gpu/drm/i915/display/intel_display_power.h 		} vlv;
vlv               716 drivers/gpu/drm/i915/display/intel_display_types.h 		} vlv;
vlv              1014 drivers/gpu/drm/i915/display/intel_display_types.h 			struct vlv_wm_state vlv;
vlv              1600 drivers/gpu/drm/i915/i915_drv.h 			struct vlv_wm_values vlv;
vlv               466 drivers/gpu/drm/i915/intel_pm.c 		dev_priv->wm.vlv.cxsr = enable;
vlv               497 drivers/gpu/drm/i915/intel_pm.c 	struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state;
vlv              1667 drivers/gpu/drm/i915/intel_pm.c 		&crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM2];
vlv              1668 drivers/gpu/drm/i915/intel_pm.c 	struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state;
vlv              1782 drivers/gpu/drm/i915/intel_pm.c 		struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level];
vlv              1806 drivers/gpu/drm/i915/intel_pm.c 		struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level];
vlv              1824 drivers/gpu/drm/i915/intel_pm.c 			      crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM2].plane[plane_id],
vlv              1825 drivers/gpu/drm/i915/intel_pm.c 			      crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM5].plane[plane_id],
vlv              1826 drivers/gpu/drm/i915/intel_pm.c 			      crtc_state->wm.vlv.raw[VLV_WM_LEVEL_DDR_DVFS].plane[plane_id]);
vlv              1835 drivers/gpu/drm/i915/intel_pm.c 		&crtc_state->wm.vlv.raw[level];
vlv              1837 drivers/gpu/drm/i915/intel_pm.c 		&crtc_state->wm.vlv.fifo_state;
vlv              1856 drivers/gpu/drm/i915/intel_pm.c 	struct vlv_wm_state *wm_state = &crtc_state->wm.vlv.optimal;
vlv              1858 drivers/gpu/drm/i915/intel_pm.c 		&crtc_state->wm.vlv.fifo_state;
vlv              1897 drivers/gpu/drm/i915/intel_pm.c 			&old_crtc_state->wm.vlv.fifo_state;
vlv              1919 drivers/gpu/drm/i915/intel_pm.c 		const struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level];
vlv              1964 drivers/gpu/drm/i915/intel_pm.c 		&crtc_state->wm.vlv.fifo_state;
vlv              2057 drivers/gpu/drm/i915/intel_pm.c 	struct vlv_wm_state *intermediate = &new_crtc_state->wm.vlv.intermediate;
vlv              2058 drivers/gpu/drm/i915/intel_pm.c 	const struct vlv_wm_state *optimal = &new_crtc_state->wm.vlv.optimal;
vlv              2063 drivers/gpu/drm/i915/intel_pm.c 	const struct vlv_wm_state *active = &old_crtc_state->wm.vlv.optimal;
vlv              2115 drivers/gpu/drm/i915/intel_pm.c 		const struct vlv_wm_state *wm_state = &crtc->wm.active.vlv;
vlv              2134 drivers/gpu/drm/i915/intel_pm.c 		const struct vlv_wm_state *wm_state = &crtc->wm.active.vlv;
vlv              2150 drivers/gpu/drm/i915/intel_pm.c 	struct vlv_wm_values *old_wm = &dev_priv->wm.vlv;
vlv              2188 drivers/gpu/drm/i915/intel_pm.c 	crtc->wm.active.vlv = crtc_state->wm.vlv.intermediate;
vlv              2203 drivers/gpu/drm/i915/intel_pm.c 	crtc->wm.active.vlv = crtc_state->wm.vlv.optimal;
vlv              6128 drivers/gpu/drm/i915/intel_pm.c 	struct vlv_wm_values *wm = &dev_priv->wm.vlv;
vlv              6174 drivers/gpu/drm/i915/intel_pm.c 		struct vlv_wm_state *active = &crtc->wm.active.vlv;
vlv              6176 drivers/gpu/drm/i915/intel_pm.c 			&crtc_state->wm.vlv.fifo_state;
vlv              6188 drivers/gpu/drm/i915/intel_pm.c 				&crtc_state->wm.vlv.raw[level];
vlv              6208 drivers/gpu/drm/i915/intel_pm.c 		crtc_state->wm.vlv.optimal = *active;
vlv              6209 drivers/gpu/drm/i915/intel_pm.c 		crtc_state->wm.vlv.intermediate = *active;
vlv              6237 drivers/gpu/drm/i915/intel_pm.c 		struct vlv_wm_state *wm_state = &crtc_state->wm.vlv.optimal;
vlv              6239 drivers/gpu/drm/i915/intel_pm.c 			&crtc_state->wm.vlv.fifo_state;
vlv              6248 drivers/gpu/drm/i915/intel_pm.c 				&crtc_state->wm.vlv.raw[level];
vlv              6262 drivers/gpu/drm/i915/intel_pm.c 		crtc_state->wm.vlv.intermediate =
vlv              6263 drivers/gpu/drm/i915/intel_pm.c 			crtc_state->wm.vlv.optimal;
vlv              6264 drivers/gpu/drm/i915/intel_pm.c 		crtc->wm.active.vlv = crtc_state->wm.vlv.optimal;