vline              87 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	uint32_t        vline;
vline              93 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	.vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
vline              98 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	.vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
vline             103 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	.vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
vline             108 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	.vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
vline             113 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	.vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
vline             118 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	.vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
vline            3231 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		if (disp_int & interrupt_status_offsets[crtc].vline)
vline              89 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	uint32_t        vline;
vline              95 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	.vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
vline             100 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	.vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
vline             105 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	.vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
vline             110 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	.vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
vline             115 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	.vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
vline             120 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	.vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
vline            3358 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		if (disp_int & interrupt_status_offsets[crtc].vline)
vline              90 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 	uint32_t	vline;
vline              96 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 	.vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
vline             101 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 	.vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
vline             106 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 	.vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
vline             111 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 	.vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
vline             116 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 	.vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
vline             121 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 	.vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
vline            2950 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 		if (disp_int & interrupt_status_offsets[crtc].vline)
vline              87 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 	uint32_t	vline;
vline              93 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 	.vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
vline              98 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 	.vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
vline             103 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 	.vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
vline             108 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 	.vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
vline             113 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 	.vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
vline             118 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 	.vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
vline            3042 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 		if (disp_int & interrupt_status_offsets[crtc].vline)
vline            3162 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		enum vline_select vline,
vline            3168 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	if (vline == VLINE0)
vline            3170 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	else if (vline == VLINE1)
vline            3191 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		enum vline_select vline)
vline            3195 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	if (vline == VLINE0) {
vline            3199 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		cal_vline_position(pipe_ctx, vline, &start_line, &end_line);
vline            3203 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	} else if (vline == VLINE1) {
vline             282 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h 	void (*setup_periodic_interrupt)(struct pipe_ctx *pipe_ctx, enum vline_select vline);
vline              23 drivers/gpu/drm/nouveau/include/nvif/cl0046.h 	__u16 vline;
vline              22 drivers/gpu/drm/nouveau/include/nvif/cl5070.h 	__u16 vline;
vline             121 drivers/gpu/drm/nouveau/nouveau_display.c 		if (args.scan.vline) {
vline             131 drivers/gpu/drm/nouveau/nouveau_display.c 		     args.scan.vtotal, args.scan.vline);
vline              72 drivers/gpu/drm/nouveau/nvkm/engine/disp/head.c 		head->func->rgpos(head, &args->v0.hline, &args->v0.vline);
vline              39 drivers/gpu/drm/nouveau/nvkm/engine/disp/head.h 	void (*rgpos)(struct nvkm_head *, u16 *hline, u16 *vline);
vline              39 drivers/gpu/drm/nouveau/nvkm/engine/disp/headgv100.c gv100_head_rgpos(struct nvkm_head *head, u16 *hline, u16 *vline)
vline              44 drivers/gpu/drm/nouveau/nvkm/engine/disp/headgv100.c 	*vline = nvkm_rd32(device, 0x616330 + hoff) & 0x0000ffff;
vline              41 drivers/gpu/drm/nouveau/nvkm/engine/disp/headnv04.c nv04_head_rgpos(struct nvkm_head *head, u16 *hline, u16 *vline)
vline              46 drivers/gpu/drm/nouveau/nvkm/engine/disp/headnv04.c 	*vline = (data & 0x0000ffff);
vline              48 drivers/gpu/drm/nouveau/nvkm/engine/disp/headnv50.c nv50_head_rgpos(struct nvkm_head *head, u16 *hline, u16 *vline)
vline              53 drivers/gpu/drm/nouveau/nvkm/engine/disp/headnv50.c 	*vline = nvkm_rd32(device, 0x616340 + hoff) & 0x0000ffff;