vlevel 2374 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c int pipe_cnt, i, pipe_idx, vlevel, vlevel_unsplit; vlevel 2458 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); vlevel 2464 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (vlevel <= context->bw_ctx.dml.soc.num_states) vlevel 2467 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c vlevel = context->bw_ctx.dml.soc.num_states + 1; vlevel 2471 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (vlevel > context->bw_ctx.dml.soc.num_states && odm_capable) vlevel 2472 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); vlevel 2474 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (vlevel > context->bw_ctx.dml.soc.num_states) vlevel 2516 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c vlevel_unsplit = vlevel; vlevel 2540 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_idx] = true; vlevel 2542 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (force_split && context->bw_ctx.dml.vba.NoOfDPP[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] == 1) vlevel 2543 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] /= 2; vlevel 2572 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c vlevel = vlevel_unsplit; vlevel 2575 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c need_split = context->bw_ctx.dml.vba.NoOfDPP[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] == 2; vlevel 2616 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c *vlevel_out = vlevel; vlevel 2633 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c int vlevel) vlevel 2642 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; vlevel 2646 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx]; vlevel 2649 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_idx]; vlevel 2655 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]]; vlevel 2658 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_split_from[i]]; vlevel 2686 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pipes[0].clks_cfg.voltage = vlevel; vlevel 2687 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz; vlevel 2688 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz; vlevel 2691 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (vlevel < 1) { vlevel 2702 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (vlevel < 2) { vlevel 2713 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (vlevel < 3) { vlevel 2724 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pipes[0].clks_cfg.voltage = vlevel; vlevel 2725 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz; vlevel 2726 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz; vlevel 2738 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c int vlevel) vlevel 2753 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] vlevel 2812 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dppclk_mhz * 1000; vlevel 2813 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dispclk_mhz * 1000; vlevel 2816 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c bool cstate_en = context->bw_ctx.dml.vba.PrefetchMode[vlevel][context->bw_ctx.dml.vba.maxMpcComb] != 2; vlevel 2845 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c int vlevel = 0; vlevel 2853 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c out = dcn20_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel); vlevel 2868 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c dcn20_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel); vlevel 2869 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel); vlevel 130 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h int vlevel); vlevel 949 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c int vlevel, vlevel 958 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c ASSERT(vlevel < dml->soc.num_states); vlevel 960 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c pipes[0].clks_cfg.voltage = vlevel; vlevel 961 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz; vlevel 962 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c pipes[0].clks_cfg.socclk_mhz = dml->soc.clock_limits[vlevel].socclk_mhz; vlevel 987 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c int vlevel, vlevel_max; vlevel 1038 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c vlevel = 0; vlevel 1040 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c vlevel = vlevel_max; vlevel 1041 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.d, vlevel 1045 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c vlevel = MIN(MAX(vlevel_req, 2), vlevel_max); vlevel 1046 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.c, vlevel 1050 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c vlevel = MIN(MAX(vlevel_req, 1), vlevel_max); vlevel 1051 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.b, vlevel 1056 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c vlevel = MIN(vlevel_req, vlevel_max); vlevel 1057 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.a, vlevel 1069 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c int vlevel = 0; vlevel 1077 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c out = dcn20_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel); vlevel 1092 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c dcn21_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel); vlevel 1093 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel); vlevel 558 virt/kvm/arm/arch_timer.c bool vlevel, plevel; vlevel 563 virt/kvm/arm/arch_timer.c vlevel = sregs->device_irq_level & KVM_ARM_DEV_EL1_VTIMER; vlevel 566 virt/kvm/arm/arch_timer.c return kvm_timer_should_fire(vtimer) != vlevel ||