vid_start        4905 drivers/net/ethernet/intel/igb/igb_main.c 	u32 vid_start = vfta_offset * 32;
vid_start        4906 drivers/net/ethernet/intel/igb/igb_main.c 	u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32);
vid_start        4911 drivers/net/ethernet/intel/igb/igb_main.c 	if (vid >= vid_start && vid < vid_end)
vid_start        4912 drivers/net/ethernet/intel/igb/igb_main.c 		vfta[(vid - vid_start) / 32] |= BIT(vid % 32);
vid_start        4926 drivers/net/ethernet/intel/igb/igb_main.c 		if (vid < vid_start || vid >= vid_end)
vid_start        4931 drivers/net/ethernet/intel/igb/igb_main.c 			vfta[(vid - vid_start) / 32] |= BIT(vid % 32);
vid_start        4620 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c 	u32 vid_start = vfta_offset * 32;
vid_start        4621 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c 	u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32);
vid_start        4631 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c 		if (vid < vid_start || vid >= vid_end)
vid_start        4636 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c 			vfta[(vid - vid_start) / 32] |= BIT(vid % 32);
vid_start        1943 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	unsigned int vid_start = MVPP2_PE_VID_FILT_RANGE_START +
vid_start        1965 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		tid = mvpp2_prs_tcam_first_free(priv, vid_start,
vid_start        1966 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 						vid_start +
vid_start         249 net/bridge/br_netlink.c static int br_fill_ifvlaninfo_range(struct sk_buff *skb, u16 vid_start,
vid_start         254 net/bridge/br_netlink.c 	if ((vid_end - vid_start) > 0) {
vid_start         256 net/bridge/br_netlink.c 		vinfo.vid = vid_start;
vid_start         268 net/bridge/br_netlink.c 		vinfo.vid = vid_start;