vgpr_init_regs   1455 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c static const u32 vgpr_init_regs[] =
vgpr_init_regs   1569 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 		(((ARRAY_SIZE(vgpr_init_regs) / 2) * 3) + 4 + 5 + 2) * 4;
vgpr_init_regs   1600 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 	for (i = 0; i < ARRAY_SIZE(vgpr_init_regs); i += 2) {
vgpr_init_regs   1602 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 		ib.ptr[ib.length_dw++] = vgpr_init_regs[i] - PACKET3_SET_SH_REG_START;
vgpr_init_regs   1603 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 		ib.ptr[ib.length_dw++] = vgpr_init_regs[i + 1];
vgpr_init_regs   4159 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c static const struct soc15_reg_entry vgpr_init_regs[] = {
vgpr_init_regs   4281 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 		((ARRAY_SIZE(vgpr_init_regs) * 3) + 4 + 5 + 2) * 4;
vgpr_init_regs   4310 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	for (i = 0; i < ARRAY_SIZE(vgpr_init_regs); i++) {
vgpr_init_regs   4312 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 		ib.ptr[ib.length_dw++] = SOC15_REG_ENTRY_OFFSET(vgpr_init_regs[i])
vgpr_init_regs   4314 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 		ib.ptr[ib.length_dw++] = vgpr_init_regs[i].reg_value;