vf_mask 236 drivers/crypto/qat/qat_common/adf_common_drv.h uint32_t vf_mask); vf_mask 238 drivers/crypto/qat/qat_common/adf_common_drv.h uint32_t vf_mask); vf_mask 114 drivers/crypto/qat/qat_common/adf_isr.c u32 vf_mask; vf_mask 117 drivers/crypto/qat/qat_common/adf_isr.c vf_mask = ((ADF_CSR_RD(pmisc_bar_addr, ADF_ERRSOU5) & vf_mask 122 drivers/crypto/qat/qat_common/adf_isr.c if (vf_mask) { vf_mask 128 drivers/crypto/qat/qat_common/adf_isr.c adf_disable_vf2pf_interrupts(accel_dev, vf_mask); vf_mask 135 drivers/crypto/qat/qat_common/adf_isr.c for_each_set_bit(i, (const unsigned long *)&vf_mask, vf_mask 136 drivers/crypto/qat/qat_common/adf_isr.c (sizeof(vf_mask) * BITS_PER_BYTE)) { vf_mask 55 drivers/crypto/qat/qat_common/adf_pf2vf_msg.c #define ADF_DH895XCC_ERRMSK3_VF2PF_L_MASK(vf_mask) ((vf_mask & 0xFFFF) << 9) vf_mask 57 drivers/crypto/qat/qat_common/adf_pf2vf_msg.c #define ADF_DH895XCC_ERRMSK5_VF2PF_U_MASK(vf_mask) (vf_mask >> 16) vf_mask 80 drivers/crypto/qat/qat_common/adf_pf2vf_msg.c u32 vf_mask) vf_mask 89 drivers/crypto/qat/qat_common/adf_pf2vf_msg.c if (vf_mask & 0xFFFF) { vf_mask 91 drivers/crypto/qat/qat_common/adf_pf2vf_msg.c reg &= ~ADF_DH895XCC_ERRMSK3_VF2PF_L_MASK(vf_mask); vf_mask 96 drivers/crypto/qat/qat_common/adf_pf2vf_msg.c if (vf_mask >> 16) { vf_mask 98 drivers/crypto/qat/qat_common/adf_pf2vf_msg.c reg &= ~ADF_DH895XCC_ERRMSK5_VF2PF_U_MASK(vf_mask); vf_mask 103 drivers/crypto/qat/qat_common/adf_pf2vf_msg.c void adf_disable_vf2pf_interrupts(struct adf_accel_dev *accel_dev, u32 vf_mask) vf_mask 112 drivers/crypto/qat/qat_common/adf_pf2vf_msg.c if (vf_mask & 0xFFFF) { vf_mask 114 drivers/crypto/qat/qat_common/adf_pf2vf_msg.c ADF_DH895XCC_ERRMSK3_VF2PF_L_MASK(vf_mask); vf_mask 119 drivers/crypto/qat/qat_common/adf_pf2vf_msg.c if (vf_mask >> 16) { vf_mask 121 drivers/crypto/qat/qat_common/adf_pf2vf_msg.c ADF_DH895XCC_ERRMSK5_VF2PF_U_MASK(vf_mask);