vdsc_cfg 258 drivers/gpu/drm/drm_dsc.c int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg) vdsc_cfg 268 drivers/gpu/drm/drm_dsc.c if (vdsc_cfg->native_420 || vdsc_cfg->native_422) { vdsc_cfg 270 drivers/gpu/drm/drm_dsc.c groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width / 2, vdsc_cfg 274 drivers/gpu/drm/drm_dsc.c vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width / 2 * vdsc_cfg 275 drivers/gpu/drm/drm_dsc.c vdsc_cfg->bits_per_pixel, vdsc_cfg 279 drivers/gpu/drm/drm_dsc.c groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width, vdsc_cfg 283 drivers/gpu/drm/drm_dsc.c vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width * vdsc_cfg 284 drivers/gpu/drm/drm_dsc.c vdsc_cfg->bits_per_pixel, vdsc_cfg 288 drivers/gpu/drm/drm_dsc.c if (vdsc_cfg->convert_rgb) vdsc_cfg 289 drivers/gpu/drm/drm_dsc.c num_extra_mux_bits = 3 * (vdsc_cfg->mux_word_size + vdsc_cfg 290 drivers/gpu/drm/drm_dsc.c (4 * vdsc_cfg->bits_per_component + 4) vdsc_cfg 292 drivers/gpu/drm/drm_dsc.c else if (vdsc_cfg->native_422) vdsc_cfg 293 drivers/gpu/drm/drm_dsc.c num_extra_mux_bits = 4 * vdsc_cfg->mux_word_size + vdsc_cfg 294 drivers/gpu/drm/drm_dsc.c (4 * vdsc_cfg->bits_per_component + 4) + vdsc_cfg 295 drivers/gpu/drm/drm_dsc.c 3 * (4 * vdsc_cfg->bits_per_component) - 2; vdsc_cfg 297 drivers/gpu/drm/drm_dsc.c num_extra_mux_bits = 3 * vdsc_cfg->mux_word_size + vdsc_cfg 298 drivers/gpu/drm/drm_dsc.c (4 * vdsc_cfg->bits_per_component + 4) + vdsc_cfg 299 drivers/gpu/drm/drm_dsc.c 2 * (4 * vdsc_cfg->bits_per_component) - 2; vdsc_cfg 301 drivers/gpu/drm/drm_dsc.c slice_bits = 8 * vdsc_cfg->slice_chunk_size * vdsc_cfg->slice_height; vdsc_cfg 304 drivers/gpu/drm/drm_dsc.c ((slice_bits - num_extra_mux_bits) % vdsc_cfg->mux_word_size)) vdsc_cfg 307 drivers/gpu/drm/drm_dsc.c if (groups_per_line < vdsc_cfg->initial_scale_value - 8) vdsc_cfg 308 drivers/gpu/drm/drm_dsc.c vdsc_cfg->initial_scale_value = groups_per_line + 8; vdsc_cfg 311 drivers/gpu/drm/drm_dsc.c if (vdsc_cfg->initial_scale_value > 8) vdsc_cfg 312 drivers/gpu/drm/drm_dsc.c vdsc_cfg->scale_decrement_interval = groups_per_line / vdsc_cfg 313 drivers/gpu/drm/drm_dsc.c (vdsc_cfg->initial_scale_value - 8); vdsc_cfg 315 drivers/gpu/drm/drm_dsc.c vdsc_cfg->scale_decrement_interval = DSC_SCALE_DECREMENT_INTERVAL_MAX; vdsc_cfg 317 drivers/gpu/drm/drm_dsc.c vdsc_cfg->final_offset = vdsc_cfg->rc_model_size - vdsc_cfg 318 drivers/gpu/drm/drm_dsc.c (vdsc_cfg->initial_xmit_delay * vdsc_cfg 319 drivers/gpu/drm/drm_dsc.c vdsc_cfg->bits_per_pixel + 8) / 16 + num_extra_mux_bits; vdsc_cfg 321 drivers/gpu/drm/drm_dsc.c if (vdsc_cfg->final_offset >= vdsc_cfg->rc_model_size) { vdsc_cfg 326 drivers/gpu/drm/drm_dsc.c final_scale = (vdsc_cfg->rc_model_size * 8) / vdsc_cfg 327 drivers/gpu/drm/drm_dsc.c (vdsc_cfg->rc_model_size - vdsc_cfg->final_offset); vdsc_cfg 328 drivers/gpu/drm/drm_dsc.c if (vdsc_cfg->slice_height > 1) vdsc_cfg 334 drivers/gpu/drm/drm_dsc.c vdsc_cfg->nfl_bpg_offset = DIV_ROUND_UP((vdsc_cfg->first_line_bpg_offset << 11), vdsc_cfg 335 drivers/gpu/drm/drm_dsc.c (vdsc_cfg->slice_height - 1)); vdsc_cfg 337 drivers/gpu/drm/drm_dsc.c vdsc_cfg->nfl_bpg_offset = 0; vdsc_cfg 340 drivers/gpu/drm/drm_dsc.c if (vdsc_cfg->nfl_bpg_offset > 65535) { vdsc_cfg 346 drivers/gpu/drm/drm_dsc.c groups_total = groups_per_line * vdsc_cfg->slice_height; vdsc_cfg 349 drivers/gpu/drm/drm_dsc.c vdsc_cfg->slice_bpg_offset = DIV_ROUND_UP(((vdsc_cfg->rc_model_size - vdsc_cfg 350 drivers/gpu/drm/drm_dsc.c vdsc_cfg->initial_offset + vdsc_cfg 361 drivers/gpu/drm/drm_dsc.c vdsc_cfg->scale_increment_interval = vdsc_cfg 362 drivers/gpu/drm/drm_dsc.c (vdsc_cfg->final_offset * (1 << 11)) / vdsc_cfg 363 drivers/gpu/drm/drm_dsc.c ((vdsc_cfg->nfl_bpg_offset + vdsc_cfg 364 drivers/gpu/drm/drm_dsc.c vdsc_cfg->slice_bpg_offset) * vdsc_cfg 371 drivers/gpu/drm/drm_dsc.c vdsc_cfg->scale_increment_interval = 0; vdsc_cfg 374 drivers/gpu/drm/drm_dsc.c if (vdsc_cfg->scale_increment_interval > 65535) { vdsc_cfg 384 drivers/gpu/drm/drm_dsc.c rbs_min = vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset + vdsc_cfg 385 drivers/gpu/drm/drm_dsc.c DIV_ROUND_UP(vdsc_cfg->initial_xmit_delay * vdsc_cfg 386 drivers/gpu/drm/drm_dsc.c vdsc_cfg->bits_per_pixel, 16) + vdsc_cfg 387 drivers/gpu/drm/drm_dsc.c groups_per_line * vdsc_cfg->first_line_bpg_offset; vdsc_cfg 389 drivers/gpu/drm/drm_dsc.c hrd_delay = DIV_ROUND_UP((rbs_min * 16), vdsc_cfg->bits_per_pixel); vdsc_cfg 390 drivers/gpu/drm/drm_dsc.c vdsc_cfg->rc_bits = (hrd_delay * vdsc_cfg->bits_per_pixel) / 16; vdsc_cfg 391 drivers/gpu/drm/drm_dsc.c vdsc_cfg->initial_dec_delay = hrd_delay - vdsc_cfg->initial_xmit_delay; vdsc_cfg 325 drivers/gpu/drm/i915/display/intel_vdsc.c struct drm_dsc_config *vdsc_cfg = &pipe_config->dp_dsc_cfg; vdsc_cfg 332 drivers/gpu/drm/i915/display/intel_vdsc.c vdsc_cfg->pic_width = pipe_config->base.adjusted_mode.crtc_hdisplay; vdsc_cfg 333 drivers/gpu/drm/i915/display/intel_vdsc.c vdsc_cfg->pic_height = pipe_config->base.adjusted_mode.crtc_vdisplay; vdsc_cfg 334 drivers/gpu/drm/i915/display/intel_vdsc.c vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width, vdsc_cfg 341 drivers/gpu/drm/i915/display/intel_vdsc.c if (vdsc_cfg->pic_height % 8 == 0) vdsc_cfg 342 drivers/gpu/drm/i915/display/intel_vdsc.c vdsc_cfg->slice_height = 8; vdsc_cfg 343 drivers/gpu/drm/i915/display/intel_vdsc.c else if (vdsc_cfg->pic_height % 4 == 0) vdsc_cfg 344 drivers/gpu/drm/i915/display/intel_vdsc.c vdsc_cfg->slice_height = 4; vdsc_cfg 346 drivers/gpu/drm/i915/display/intel_vdsc.c vdsc_cfg->slice_height = 2; vdsc_cfg 349 drivers/gpu/drm/i915/display/intel_vdsc.c vdsc_cfg->dsc_version_major = vdsc_cfg 352 drivers/gpu/drm/i915/display/intel_vdsc.c vdsc_cfg->dsc_version_minor = vdsc_cfg 357 drivers/gpu/drm/i915/display/intel_vdsc.c vdsc_cfg->convert_rgb = intel_dp->dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] & vdsc_cfg 365 drivers/gpu/drm/i915/display/intel_vdsc.c if (vdsc_cfg->dsc_version_minor == 2) vdsc_cfg 366 drivers/gpu/drm/i915/display/intel_vdsc.c vdsc_cfg->line_buf_depth = (line_buf_depth == DSC_1_2_MAX_LINEBUF_DEPTH_BITS) ? vdsc_cfg 369 drivers/gpu/drm/i915/display/intel_vdsc.c vdsc_cfg->line_buf_depth = (line_buf_depth > DSC_1_1_MAX_LINEBUF_DEPTH_BITS) ? vdsc_cfg 373 drivers/gpu/drm/i915/display/intel_vdsc.c vdsc_cfg->simple_422 = false; vdsc_cfg 375 drivers/gpu/drm/i915/display/intel_vdsc.c vdsc_cfg->vbr_enable = false; vdsc_cfg 376 drivers/gpu/drm/i915/display/intel_vdsc.c vdsc_cfg->block_pred_enable = vdsc_cfg 381 drivers/gpu/drm/i915/display/intel_vdsc.c vdsc_cfg->bits_per_pixel = compressed_bpp << 4; vdsc_cfg 382 drivers/gpu/drm/i915/display/intel_vdsc.c vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3; vdsc_cfg 390 drivers/gpu/drm/i915/display/intel_vdsc.c vdsc_cfg->rc_buf_thresh[i] = rc_buf_thresh[i] >> 6; vdsc_cfg 398 drivers/gpu/drm/i915/display/intel_vdsc.c vdsc_cfg->rc_buf_thresh[12] = 0x7C; vdsc_cfg 399 drivers/gpu/drm/i915/display/intel_vdsc.c vdsc_cfg->rc_buf_thresh[13] = 0x7D; vdsc_cfg 404 drivers/gpu/drm/i915/display/intel_vdsc.c get_column_index_for_rc_params(vdsc_cfg->bits_per_component); vdsc_cfg 409 drivers/gpu/drm/i915/display/intel_vdsc.c vdsc_cfg->first_line_bpg_offset = vdsc_cfg 411 drivers/gpu/drm/i915/display/intel_vdsc.c vdsc_cfg->initial_xmit_delay = vdsc_cfg 413 drivers/gpu/drm/i915/display/intel_vdsc.c vdsc_cfg->initial_offset = vdsc_cfg 415 drivers/gpu/drm/i915/display/intel_vdsc.c vdsc_cfg->flatness_min_qp = vdsc_cfg 417 drivers/gpu/drm/i915/display/intel_vdsc.c vdsc_cfg->flatness_max_qp = vdsc_cfg 419 drivers/gpu/drm/i915/display/intel_vdsc.c vdsc_cfg->rc_quant_incr_limit0 = vdsc_cfg 421 drivers/gpu/drm/i915/display/intel_vdsc.c vdsc_cfg->rc_quant_incr_limit1 = vdsc_cfg 425 drivers/gpu/drm/i915/display/intel_vdsc.c vdsc_cfg->rc_range_params[i].range_min_qp = vdsc_cfg 427 drivers/gpu/drm/i915/display/intel_vdsc.c vdsc_cfg->rc_range_params[i].range_max_qp = vdsc_cfg 433 drivers/gpu/drm/i915/display/intel_vdsc.c vdsc_cfg->rc_range_params[i].range_bpg_offset = vdsc_cfg 444 drivers/gpu/drm/i915/display/intel_vdsc.c if (vdsc_cfg->bits_per_component == 8 || vdsc_cfg 445 drivers/gpu/drm/i915/display/intel_vdsc.c vdsc_cfg->bits_per_component == 10) vdsc_cfg 446 drivers/gpu/drm/i915/display/intel_vdsc.c vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC; vdsc_cfg 447 drivers/gpu/drm/i915/display/intel_vdsc.c else if (vdsc_cfg->bits_per_component == 12) vdsc_cfg 448 drivers/gpu/drm/i915/display/intel_vdsc.c vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_12_BPC; vdsc_cfg 451 drivers/gpu/drm/i915/display/intel_vdsc.c vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST; vdsc_cfg 453 drivers/gpu/drm/i915/display/intel_vdsc.c vdsc_cfg->initial_scale_value = (vdsc_cfg->rc_model_size << 3) / vdsc_cfg 454 drivers/gpu/drm/i915/display/intel_vdsc.c (vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset); vdsc_cfg 456 drivers/gpu/drm/i915/display/intel_vdsc.c return drm_dsc_compute_rc_parameters(vdsc_cfg); vdsc_cfg 488 drivers/gpu/drm/i915/display/intel_vdsc.c const struct drm_dsc_config *vdsc_cfg = &crtc_state->dp_dsc_cfg; vdsc_cfg 498 drivers/gpu/drm/i915/display/intel_vdsc.c pps_val = DSC_VER_MAJ | vdsc_cfg->dsc_version_minor << vdsc_cfg 500 drivers/gpu/drm/i915/display/intel_vdsc.c vdsc_cfg->bits_per_component << DSC_BPC_SHIFT | vdsc_cfg 501 drivers/gpu/drm/i915/display/intel_vdsc.c vdsc_cfg->line_buf_depth << DSC_LINE_BUF_DEPTH_SHIFT; vdsc_cfg 502 drivers/gpu/drm/i915/display/intel_vdsc.c if (vdsc_cfg->block_pred_enable) vdsc_cfg 504 drivers/gpu/drm/i915/display/intel_vdsc.c if (vdsc_cfg->convert_rgb) vdsc_cfg 506 drivers/gpu/drm/i915/display/intel_vdsc.c if (vdsc_cfg->simple_422) vdsc_cfg 508 drivers/gpu/drm/i915/display/intel_vdsc.c if (vdsc_cfg->vbr_enable) vdsc_cfg 528 drivers/gpu/drm/i915/display/intel_vdsc.c pps_val |= DSC_BPP(vdsc_cfg->bits_per_pixel); vdsc_cfg 547 drivers/gpu/drm/i915/display/intel_vdsc.c pps_val |= DSC_PIC_HEIGHT(vdsc_cfg->pic_height) | vdsc_cfg 548 drivers/gpu/drm/i915/display/intel_vdsc.c DSC_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances); vdsc_cfg 567 drivers/gpu/drm/i915/display/intel_vdsc.c pps_val |= DSC_SLICE_HEIGHT(vdsc_cfg->slice_height) | vdsc_cfg 568 drivers/gpu/drm/i915/display/intel_vdsc.c DSC_SLICE_WIDTH(vdsc_cfg->slice_width); vdsc_cfg 587 drivers/gpu/drm/i915/display/intel_vdsc.c pps_val |= DSC_INITIAL_XMIT_DELAY(vdsc_cfg->initial_xmit_delay) | vdsc_cfg 588 drivers/gpu/drm/i915/display/intel_vdsc.c DSC_INITIAL_DEC_DELAY(vdsc_cfg->initial_dec_delay); vdsc_cfg 607 drivers/gpu/drm/i915/display/intel_vdsc.c pps_val |= DSC_SCALE_INC_INT(vdsc_cfg->scale_increment_interval) | vdsc_cfg 608 drivers/gpu/drm/i915/display/intel_vdsc.c DSC_SCALE_DEC_INT(vdsc_cfg->scale_decrement_interval); vdsc_cfg 627 drivers/gpu/drm/i915/display/intel_vdsc.c pps_val |= DSC_INITIAL_SCALE_VALUE(vdsc_cfg->initial_scale_value) | vdsc_cfg 628 drivers/gpu/drm/i915/display/intel_vdsc.c DSC_FIRST_LINE_BPG_OFFSET(vdsc_cfg->first_line_bpg_offset) | vdsc_cfg 629 drivers/gpu/drm/i915/display/intel_vdsc.c DSC_FLATNESS_MIN_QP(vdsc_cfg->flatness_min_qp) | vdsc_cfg 630 drivers/gpu/drm/i915/display/intel_vdsc.c DSC_FLATNESS_MAX_QP(vdsc_cfg->flatness_max_qp); vdsc_cfg 649 drivers/gpu/drm/i915/display/intel_vdsc.c pps_val |= DSC_SLICE_BPG_OFFSET(vdsc_cfg->slice_bpg_offset) | vdsc_cfg 650 drivers/gpu/drm/i915/display/intel_vdsc.c DSC_NFL_BPG_OFFSET(vdsc_cfg->nfl_bpg_offset); vdsc_cfg 669 drivers/gpu/drm/i915/display/intel_vdsc.c pps_val |= DSC_FINAL_OFFSET(vdsc_cfg->final_offset) | vdsc_cfg 670 drivers/gpu/drm/i915/display/intel_vdsc.c DSC_INITIAL_OFFSET(vdsc_cfg->initial_offset); vdsc_cfg 709 drivers/gpu/drm/i915/display/intel_vdsc.c pps_val |= DSC_RC_QUANT_INC_LIMIT0(vdsc_cfg->rc_quant_incr_limit0) | vdsc_cfg 710 drivers/gpu/drm/i915/display/intel_vdsc.c DSC_RC_QUANT_INC_LIMIT1(vdsc_cfg->rc_quant_incr_limit1) | vdsc_cfg 731 drivers/gpu/drm/i915/display/intel_vdsc.c pps_val |= DSC_SLICE_CHUNK_SIZE(vdsc_cfg->slice_chunk_size) | vdsc_cfg 732 drivers/gpu/drm/i915/display/intel_vdsc.c DSC_SLICE_PER_LINE((vdsc_cfg->pic_width / num_vdsc_instances) / vdsc_cfg 733 drivers/gpu/drm/i915/display/intel_vdsc.c vdsc_cfg->slice_width) | vdsc_cfg 734 drivers/gpu/drm/i915/display/intel_vdsc.c DSC_SLICE_ROW_PER_FRAME(vdsc_cfg->pic_height / vdsc_cfg 735 drivers/gpu/drm/i915/display/intel_vdsc.c vdsc_cfg->slice_height); vdsc_cfg 756 drivers/gpu/drm/i915/display/intel_vdsc.c (u32)(vdsc_cfg->rc_buf_thresh[i] << vdsc_cfg 801 drivers/gpu/drm/i915/display/intel_vdsc.c (u32)(((vdsc_cfg->rc_range_params[i].range_bpg_offset << vdsc_cfg 803 drivers/gpu/drm/i915/display/intel_vdsc.c (vdsc_cfg->rc_range_params[i].range_max_qp << vdsc_cfg 805 drivers/gpu/drm/i915/display/intel_vdsc.c (vdsc_cfg->rc_range_params[i].range_min_qp << vdsc_cfg 888 drivers/gpu/drm/i915/display/intel_vdsc.c const struct drm_dsc_config *vdsc_cfg = &crtc_state->dp_dsc_cfg; vdsc_cfg 895 drivers/gpu/drm/i915/display/intel_vdsc.c drm_dsc_pps_payload_pack(&dp_dsc_pps_sdp.pps_payload, vdsc_cfg); vdsc_cfg 607 include/drm/drm_dsc.h int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg);