vddc_table        562 drivers/gpu/drm/amd/amdgpu/si_dpm.h 	struct vddc_table_entry vddc_table[MAX_NO_VREG_STEPS];
vddc_table        643 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			&data->dpm_table.vddc_table,
vddc_table        719 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		data->dpm_table.vddc_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].v;
vddc_table        720 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		data->dpm_table.vddc_table.dpm_levels[i].param1 = std_voltage_table->entries[i].Leakage;
vddc_table        722 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		data->dpm_table.vddc_table.dpm_levels[i].enabled = 1;
vddc_table        725 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	data->dpm_table.vddc_table.count = allowed_vdd_sclk_table->count;
vddc_table        107 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h 	struct smu7_single_dpm_table  vddc_table;
vddc_table        441 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	struct phm_clock_voltage_dependency_table *vddc_table =
vddc_table        463 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	PP_ASSERT_WITH_CODE((vddc_table->count <= SMU8_MAX_HARDWARE_POWERLEVELS),
vddc_table        478 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 			(i < vddc_table->count) ? (uint8_t)vddc_table->entries[i].v : 0;
vddc_table        480 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 			(i < vddc_table->count) ? vddc_table->entries[i].clk : 0;
vddc_table        539 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c 	struct phm_ppt_v1_clock_voltage_dependency_table *vddc_table;
vddc_table        555 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c 	vddc_table = table_info->vdd_dep_on_sclk;
vddc_table        556 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c 	for (i = 0; i < vddc_table->count; i++) {
vddc_table        557 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c 		if (req_vddc <= vddc_table->entries[i].vddc) {
vddc_table        558 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c 			req_volt = (((uint32_t)vddc_table->entries[i].vddc) * VOLTAGE_SCALE);
vddc_table       1153 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		const ATOM_Vega10_Voltage_Lookup_Table *vddc_table =
vddc_table       1158 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 				&pp_table_info->vddc_lookup_table, vddc_table, 8);
vddc_table       3470 drivers/gpu/drm/radeon/ci_dpm.c 				  &pi->dpm_table.vddc_table,
vddc_table       3506 drivers/gpu/drm/radeon/ci_dpm.c 		pi->dpm_table.vddc_table.dpm_levels[i].value =
vddc_table       3508 drivers/gpu/drm/radeon/ci_dpm.c 		pi->dpm_table.vddc_table.dpm_levels[i].param1 =
vddc_table       3510 drivers/gpu/drm/radeon/ci_dpm.c 		pi->dpm_table.vddc_table.dpm_levels[i].enabled = true;
vddc_table       3512 drivers/gpu/drm/radeon/ci_dpm.c 	pi->dpm_table.vddc_table.count = allowed_sclk_vddc_table->count;
vddc_table       3787 drivers/gpu/drm/radeon/ci_dpm.c 	struct radeon_clock_voltage_dependency_table *vddc_table =
vddc_table       3802 drivers/gpu/drm/radeon/ci_dpm.c 	for (i = 0; i < vddc_table->count; i++) {
vddc_table       3803 drivers/gpu/drm/radeon/ci_dpm.c 		if (requested_voltage <= vddc_table->entries[i].v) {
vddc_table       3804 drivers/gpu/drm/radeon/ci_dpm.c 			requested_voltage = vddc_table->entries[i].v;
vddc_table         72 drivers/gpu/drm/radeon/ci_dpm.h 	struct ci_single_dpm_table vddc_table;
vddc_table        578 drivers/gpu/drm/radeon/rv770_dpm.c 		if (vddc <= pi->vddc_table[i].vddc) {
vddc_table        579 drivers/gpu/drm/radeon/rv770_dpm.c 			voltage->index = pi->vddc_table[i].vddc_index;
vddc_table       1120 drivers/gpu/drm/radeon/rv770_dpm.c 		table->highSMIO[pi->vddc_table[i].vddc_index] =
vddc_table       1121 drivers/gpu/drm/radeon/rv770_dpm.c 			pi->vddc_table[i].high_smio;
vddc_table       1122 drivers/gpu/drm/radeon/rv770_dpm.c 		table->lowSMIO[pi->vddc_table[i].vddc_index] =
vddc_table       1123 drivers/gpu/drm/radeon/rv770_dpm.c 			cpu_to_be32(pi->vddc_table[i].low_smio);
vddc_table       1133 drivers/gpu/drm/radeon/rv770_dpm.c 	       pi->vddc_table[i].vddc));
vddc_table       1137 drivers/gpu/drm/radeon/rv770_dpm.c 		pi->vddc_table[i].vddc_index;
vddc_table       1251 drivers/gpu/drm/radeon/rv770_dpm.c 		pi->vddc_table[i].vddc = (u16)(min + i * step);
vddc_table       1253 drivers/gpu/drm/radeon/rv770_dpm.c 						      pi->vddc_table[i].vddc,
vddc_table       1256 drivers/gpu/drm/radeon/rv770_dpm.c 		pi->vddc_table[i].low_smio = gpio_pins & gpio_mask;
vddc_table       1257 drivers/gpu/drm/radeon/rv770_dpm.c 		pi->vddc_table[i].high_smio = 0;
vddc_table       1260 drivers/gpu/drm/radeon/rv770_dpm.c 			if ((pi->vddc_table[i].low_smio !=
vddc_table       1261 drivers/gpu/drm/radeon/rv770_dpm.c 			     pi->vddc_table[i - 1].low_smio ) ||
vddc_table       1262 drivers/gpu/drm/radeon/rv770_dpm.c 			     (pi->vddc_table[i].high_smio !=
vddc_table       1263 drivers/gpu/drm/radeon/rv770_dpm.c 			      pi->vddc_table[i - 1].high_smio))
vddc_table       1266 drivers/gpu/drm/radeon/rv770_dpm.c 		pi->vddc_table[i].vddc_index = vddc_index;
vddc_table        106 drivers/gpu/drm/radeon/rv770_dpm.h 	struct vddc_table_entry vddc_table[MAX_NO_VREG_STEPS];