vddc_phase_shed_table 4488 drivers/gpu/drm/amd/amdgpu/si_dpm.c 						    VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table);
vddc_phase_shed_table 4492 drivers/gpu/drm/amd/amdgpu/si_dpm.c 		if ((si_pi->vddc_phase_shed_table.count == 0) ||
vddc_phase_shed_table 4493 drivers/gpu/drm/amd/amdgpu/si_dpm.c 		    (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS))
vddc_phase_shed_table 4555 drivers/gpu/drm/amd/amdgpu/si_dpm.c 			if (si_validate_phase_shedding_tables(adev, &si_pi->vddc_phase_shed_table,
vddc_phase_shed_table 4557 drivers/gpu/drm/amd/amdgpu/si_dpm.c 				si_populate_smc_voltage_table(adev, &si_pi->vddc_phase_shed_table, table);
vddc_phase_shed_table 4560 drivers/gpu/drm/amd/amdgpu/si_dpm.c 					cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low);
vddc_phase_shed_table 4563 drivers/gpu/drm/amd/amdgpu/si_dpm.c 							   (u32)si_pi->vddc_phase_shed_table.phase_delay);
vddc_phase_shed_table  964 drivers/gpu/drm/amd/amdgpu/si_dpm.h 	struct atom_voltage_table vddc_phase_shed_table;
vddc_phase_shed_table 4026 drivers/gpu/drm/radeon/si_dpm.c 						    VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table);
vddc_phase_shed_table 4030 drivers/gpu/drm/radeon/si_dpm.c 		if ((si_pi->vddc_phase_shed_table.count == 0) ||
vddc_phase_shed_table 4031 drivers/gpu/drm/radeon/si_dpm.c 		    (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS))
vddc_phase_shed_table 4093 drivers/gpu/drm/radeon/si_dpm.c 			if (si_validate_phase_shedding_tables(rdev, &si_pi->vddc_phase_shed_table,
vddc_phase_shed_table 4095 drivers/gpu/drm/radeon/si_dpm.c 				si_populate_smc_voltage_table(rdev, &si_pi->vddc_phase_shed_table, table);
vddc_phase_shed_table 4098 drivers/gpu/drm/radeon/si_dpm.c 					cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low);
vddc_phase_shed_table 4101 drivers/gpu/drm/radeon/si_dpm.c 							   (u32)si_pi->vddc_phase_shed_table.phase_delay);
vddc_phase_shed_table  157 drivers/gpu/drm/radeon/si_dpm.h 	struct atom_voltage_table vddc_phase_shed_table;