vddc_phase_shed_limits_table 1564 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 			hwmgr->dyn_state.vddc_phase_shed_limits_table = table;
vddc_phase_shed_limits_table 1697 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	kfree(hwmgr->dyn_state.vddc_phase_shed_limits_table);
vddc_phase_shed_limits_table 1698 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	hwmgr->dyn_state.vddc_phase_shed_limits_table = NULL;
vddc_phase_shed_limits_table 2434 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	tmp = smu7_patch_vddc_shed_limit(hwmgr, hwmgr->dyn_state.vddc_phase_shed_limits_table);
vddc_phase_shed_limits_table  635 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	struct phm_phase_shedding_limits_table  *vddc_phase_shed_limits_table;
vddc_phase_shed_limits_table  429 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 				hwmgr->dyn_state.vddc_phase_shed_limits_table,
vddc_phase_shed_limits_table 1213 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		ci_populate_phase_value_based_on_mclk(hwmgr, hwmgr->dyn_state.vddc_phase_shed_limits_table,
vddc_phase_shed_limits_table  913 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 				hwmgr->dyn_state.vddc_phase_shed_limits_table,
vddc_phase_shed_limits_table 1261 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		iceland_populate_phase_value_based_on_mclk(hwmgr, hwmgr->dyn_state.vddc_phase_shed_limits_table,