vddc_phase_shed_control 4486 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (si_pi->vddc_phase_shed_control) { vddc_phase_shed_control 4490 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->vddc_phase_shed_control = false; vddc_phase_shed_control 4494 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->vddc_phase_shed_control = false; vddc_phase_shed_control 4554 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (si_pi->vddc_phase_shed_control) { vddc_phase_shed_control 4565 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->vddc_phase_shed_control = false; vddc_phase_shed_control 4906 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (si_pi->vddc_phase_shed_control) vddc_phase_shed_control 4990 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (si_pi->vddc_phase_shed_control) { vddc_phase_shed_control 5018 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (si_pi->vddc_phase_shed_control) vddc_phase_shed_control 5530 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (si_pi->vddc_phase_shed_control) { vddc_phase_shed_control 7416 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->vddc_phase_shed_control = vddc_phase_shed_control 977 drivers/gpu/drm/amd/amdgpu/si_dpm.h bool vddc_phase_shed_control; vddc_phase_shed_control 1599 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c data->vddc_phase_shed_control = ((tmp3 << 1) | (tmp3 >> 1)) & 0x3; vddc_phase_shed_control 1601 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c data->vddc_phase_shed_control = 1; vddc_phase_shed_control 1603 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c data->vddc_phase_shed_control = 0; vddc_phase_shed_control 287 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h uint8_t vddc_phase_shed_control; vddc_phase_shed_control 427 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c if (data->vddc_phase_shed_control) vddc_phase_shed_control 1212 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c if (data->vddc_phase_shed_control) { vddc_phase_shed_control 1397 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c table->ACPILevel.MinVddcPhases = data->vddc_phase_shed_control ? 0 : 1; vddc_phase_shed_control 911 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c if (data->vddc_phase_shed_control) vddc_phase_shed_control 1260 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c if (data->vddc_phase_shed_control) { vddc_phase_shed_control 1428 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c uint32_t vddc_phase_shed_control = 0; vddc_phase_shed_control 1445 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c table->ACPILevel.MinVddcPhases = vddc_phase_shed_control ? 0 : 1; vddc_phase_shed_control 749 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c state->VddcPhase = data->vddc_phase_shed_control ^ 0x3; vddc_phase_shed_control 751 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c state->VddcPhase = (data->vddc_phase_shed_control) ? 0 : 1; vddc_phase_shed_control 552 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c state->VddcPhase = data->vddc_phase_shed_control ^ 0x3; vddc_phase_shed_control 2909 drivers/gpu/drm/radeon/ci_dpm.c if (pi->vddc_phase_shed_control) vddc_phase_shed_control 3008 drivers/gpu/drm/radeon/ci_dpm.c table->ACPILevel.MinVddcPhases = pi->vddc_phase_shed_control ? 0 : 1; vddc_phase_shed_control 3150 drivers/gpu/drm/radeon/ci_dpm.c state->VddcPhase = pi->vddc_phase_shed_control ? 0 : 1; vddc_phase_shed_control 3238 drivers/gpu/drm/radeon/ci_dpm.c if (pi->vddc_phase_shed_control) vddc_phase_shed_control 5902 drivers/gpu/drm/radeon/ci_dpm.c pi->vddc_phase_shed_control = true; vddc_phase_shed_control 236 drivers/gpu/drm/radeon/ci_dpm.h bool vddc_phase_shed_control; vddc_phase_shed_control 4024 drivers/gpu/drm/radeon/si_dpm.c if (si_pi->vddc_phase_shed_control) { vddc_phase_shed_control 4028 drivers/gpu/drm/radeon/si_dpm.c si_pi->vddc_phase_shed_control = false; vddc_phase_shed_control 4032 drivers/gpu/drm/radeon/si_dpm.c si_pi->vddc_phase_shed_control = false; vddc_phase_shed_control 4092 drivers/gpu/drm/radeon/si_dpm.c if (si_pi->vddc_phase_shed_control) { vddc_phase_shed_control 4103 drivers/gpu/drm/radeon/si_dpm.c si_pi->vddc_phase_shed_control = false; vddc_phase_shed_control 4442 drivers/gpu/drm/radeon/si_dpm.c if (si_pi->vddc_phase_shed_control) vddc_phase_shed_control 4528 drivers/gpu/drm/radeon/si_dpm.c if (si_pi->vddc_phase_shed_control) { vddc_phase_shed_control 4555 drivers/gpu/drm/radeon/si_dpm.c if (si_pi->vddc_phase_shed_control) vddc_phase_shed_control 5068 drivers/gpu/drm/radeon/si_dpm.c if (si_pi->vddc_phase_shed_control) { vddc_phase_shed_control 7026 drivers/gpu/drm/radeon/si_dpm.c si_pi->vddc_phase_shed_control = vddc_phase_shed_control 170 drivers/gpu/drm/radeon/si_dpm.h bool vddc_phase_shed_control;