vddc_dependency_on_mclk  356 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c 			ret = amdgpu_parse_clk_voltage_dep_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
vddc_dependency_on_mclk  725 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c 	kfree(dyn_state->vddc_dependency_on_mclk.entries);
vddc_dependency_on_mclk  210 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h 	struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk;
vddc_dependency_on_mclk 3512 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
vddc_dependency_on_mclk 3620 drivers/gpu/drm/amd/amdgpu/si_dpm.c 		btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
vddc_dependency_on_mclk 4439 drivers/gpu/drm/amd/amdgpu/si_dpm.c 						&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
vddc_dependency_on_mclk 6362 drivers/gpu/drm/amd/amdgpu/si_dpm.c 								&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
vddc_dependency_on_mclk 1241 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	hwmgr->dyn_state.vddc_dependency_on_mclk = NULL;
vddc_dependency_on_mclk 1351 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 				&hwmgr->dyn_state.vddc_dependency_on_mclk, table);
vddc_dependency_on_mclk 1362 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 		if (result == 0 && (NULL != hwmgr->dyn_state.vddc_dependency_on_mclk) &&
vddc_dependency_on_mclk 1363 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 			(0 != hwmgr->dyn_state.vddc_dependency_on_mclk->count))
vddc_dependency_on_mclk 1365 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 					hwmgr->dyn_state.vddc_dependency_on_mclk);
vddc_dependency_on_mclk 1682 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	kfree(hwmgr->dyn_state.vddc_dependency_on_mclk);
vddc_dependency_on_mclk 1683 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	hwmgr->dyn_state.vddc_dependency_on_mclk = NULL;
vddc_dependency_on_mclk  316 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 					hwmgr->dyn_state.vddc_dependency_on_mclk);
vddc_dependency_on_mclk  674 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		hwmgr->dyn_state.vddc_dependency_on_mclk;
vddc_dependency_on_mclk 2406 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	tmp = smu7_patch_vddc(hwmgr, hwmgr->dyn_state.vddc_dependency_on_mclk);
vddc_dependency_on_mclk 2459 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct phm_clock_voltage_dependency_table *allowed_mclk_vddc_table = hwmgr->dyn_state.vddc_dependency_on_mclk;
vddc_dependency_on_mclk 4707 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		mclk_table = hwmgr->dyn_state.vddc_dependency_on_mclk;
vddc_dependency_on_mclk  623 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	struct phm_clock_voltage_dependency_table *vddc_dependency_on_mclk;
vddc_dependency_on_mclk 1185 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	if (hwmgr->dyn_state.vddc_dependency_on_mclk != NULL) {
vddc_dependency_on_mclk 1187 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 			hwmgr->dyn_state.vddc_dependency_on_mclk, memory_clock, &memory_level->MinVddc);
vddc_dependency_on_mclk 1868 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	count = (uint8_t)(hwmgr->dyn_state.vddc_dependency_on_mclk->count);
vddc_dependency_on_mclk 1871 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		if (hwmgr->dyn_state.vddc_dependency_on_mclk->entries[level].clk
vddc_dependency_on_mclk 1240 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	if (hwmgr->dyn_state.vddc_dependency_on_mclk != NULL) {
vddc_dependency_on_mclk 1242 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 			hwmgr->dyn_state.vddc_dependency_on_mclk, memory_clock, &memory_level->MinVddc);
vddc_dependency_on_mclk 1836 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	count = (uint8_t)(hwmgr->dyn_state.vddc_dependency_on_mclk->count);
vddc_dependency_on_mclk 1839 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		if (hwmgr->dyn_state.vddc_dependency_on_mclk->entries[level].clk
vddc_dependency_on_mclk 2214 drivers/gpu/drm/radeon/btc_dpm.c 	btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
vddc_dependency_on_mclk 2223 drivers/gpu/drm/radeon/btc_dpm.c 	btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
vddc_dependency_on_mclk 2232 drivers/gpu/drm/radeon/btc_dpm.c 	btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
vddc_dependency_on_mclk 2147 drivers/gpu/drm/radeon/ci_dpm.c 						&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
vddc_dependency_on_mclk 2601 drivers/gpu/drm/radeon/ci_dpm.c 	for (level = 0; level < rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.count; level++) {
vddc_dependency_on_mclk 2602 drivers/gpu/drm/radeon/ci_dpm.c 		if (rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries[level].clk >=
vddc_dependency_on_mclk 2883 drivers/gpu/drm/radeon/ci_dpm.c 	if (rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries) {
vddc_dependency_on_mclk 2885 drivers/gpu/drm/radeon/ci_dpm.c 						    &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
vddc_dependency_on_mclk 3447 drivers/gpu/drm/radeon/ci_dpm.c 		&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk;
vddc_dependency_on_mclk 4923 drivers/gpu/drm/radeon/ci_dpm.c 		&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk;
vddc_dependency_on_mclk 5069 drivers/gpu/drm/radeon/ci_dpm.c 								  &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
vddc_dependency_on_mclk  881 drivers/gpu/drm/radeon/ni_dpm.c 		btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
vddc_dependency_on_mclk 1017 drivers/gpu/drm/radeon/ni_dpm.c 								&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
vddc_dependency_on_mclk  946 drivers/gpu/drm/radeon/r600_dpm.c 			ret = r600_parse_clk_voltage_dep_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
vddc_dependency_on_mclk  963 drivers/gpu/drm/radeon/r600_dpm.c 				kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries);
vddc_dependency_on_mclk 1304 drivers/gpu/drm/radeon/r600_dpm.c 	kfree(dyn_state->vddc_dependency_on_mclk.entries);
vddc_dependency_on_mclk 1472 drivers/gpu/drm/radeon/radeon.h 	struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk;
vddc_dependency_on_mclk 3053 drivers/gpu/drm/radeon/si_dpm.c 	btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
vddc_dependency_on_mclk 3161 drivers/gpu/drm/radeon/si_dpm.c 		btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
vddc_dependency_on_mclk 3977 drivers/gpu/drm/radeon/si_dpm.c 						&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
vddc_dependency_on_mclk 5908 drivers/gpu/drm/radeon/si_dpm.c 								&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk);