vdd_dep_on_mclk   795 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 	pp_table_information->vdd_dep_on_mclk = NULL;
vdd_dep_on_mclk   814 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 		&pp_table_information->vdd_dep_on_mclk, mclk_dep_table);
vdd_dep_on_mclk   833 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 	if (result == 0 && (NULL != pp_table_information->vdd_dep_on_mclk)
vdd_dep_on_mclk   834 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 		&& (0 != pp_table_information->vdd_dep_on_mclk->count))
vdd_dep_on_mclk   836 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 		pp_table_information->vdd_dep_on_mclk);
vdd_dep_on_mclk  1117 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 	kfree(pp_table_information->vdd_dep_on_mclk);
vdd_dep_on_mclk  1118 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 	pp_table_information->vdd_dep_on_mclk = NULL;
vdd_dep_on_mclk   460 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_mclk,
vdd_dep_on_mclk  1001 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		pclk_vol_table = pinfo->vdd_dep_on_mclk;
vdd_dep_on_mclk  1057 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		pclk_vol_table = pinfo->vdd_dep_on_mclk;
vdd_dep_on_mclk   202 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h 	struct smu10_voltage_dependency_table    *vdd_dep_on_mclk;
vdd_dep_on_mclk   268 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 					table_info->vdd_dep_on_mclk);
vdd_dep_on_mclk   288 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 					table_info->vdd_dep_on_mclk);
vdd_dep_on_mclk   768 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	dep_mclk_table = table_info->vdd_dep_on_mclk;
vdd_dep_on_mclk   835 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	dep_mclk_table = table_info->vdd_dep_on_mclk;
vdd_dep_on_mclk   922 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	dep_table = table_info->vdd_dep_on_mclk;
vdd_dep_on_mclk  1854 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			table_info->vdd_dep_on_mclk;
vdd_dep_on_mclk  1933 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	phm_ppt_v1_clock_voltage_dependency_table *mclk_table = pptable_info->vdd_dep_on_mclk;
vdd_dep_on_mclk  2078 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 						table_info->vdd_dep_on_mclk;
vdd_dep_on_mclk  2122 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		dep_mclk_table = table_info->vdd_dep_on_mclk;
vdd_dep_on_mclk  3225 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			table_info->vdd_dep_on_mclk;
vdd_dep_on_mclk  4699 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		dep_mclk_table = table_info->vdd_dep_on_mclk;
vdd_dep_on_mclk   330 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	dep_table[1] = table_info->vdd_dep_on_mclk;
vdd_dep_on_mclk   333 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	od_table[1] = (struct phm_ppt_v1_clock_voltage_dependency_table *)&odn_table->vdd_dep_on_mclk;
vdd_dep_on_mclk   668 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			table_info->vdd_dep_on_mclk;
vdd_dep_on_mclk   775 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			table_info->vdd_dep_on_mclk;
vdd_dep_on_mclk  1163 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 				table_info->vdd_dep_on_mclk,
vdd_dep_on_mclk  1172 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 				table_info->vdd_dep_on_mclk,
vdd_dep_on_mclk  1303 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			table_info->vdd_dep_on_mclk;
vdd_dep_on_mclk  1765 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 					&data->odn_dpm_table.vdd_dep_on_mclk;
vdd_dep_on_mclk  1767 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		dep_on_mclk = table_info->vdd_dep_on_mclk;
vdd_dep_on_mclk  2465 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	dep_table = table_info->vdd_dep_on_mclk;
vdd_dep_on_mclk  2466 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	odn_dep_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dep_on_mclk);
vdd_dep_on_mclk  3346 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	odn_clk_table = &odn_table->vdd_dep_on_mclk;
vdd_dep_on_mclk  3482 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	vdd_dep_table_on_mclk  = table_info->vdd_dep_on_mclk;
vdd_dep_on_mclk  3918 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table = table_info->vdd_dep_on_mclk;
vdd_dep_on_mclk  4039 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		table_info->vdd_dep_on_mclk->count > VEGA10_UMD_PSTATE_MCLK_LEVEL) {
vdd_dep_on_mclk  4044 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		hwmgr->pstate_mclk = table_info->vdd_dep_on_mclk->entries[VEGA10_UMD_PSTATE_MCLK_LEVEL].clk;
vdd_dep_on_mclk  4054 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		*mclk_mask = table_info->vdd_dep_on_mclk->count - 1;
vdd_dep_on_mclk  4234 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			table_info->vdd_dep_on_mclk;
vdd_dep_on_mclk  4321 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		dep_table = table_info->vdd_dep_on_mclk;
vdd_dep_on_mclk  4555 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			podn_vdd_dep = &data->odn_dpm_table.vdd_dep_on_mclk;
vdd_dep_on_mclk  5104 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		podn_vdd_dep = &data->odn_dpm_table.vdd_dep_on_mclk;
vdd_dep_on_mclk  5182 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		podn_vdd_dep_table = &data->odn_dpm_table.vdd_dep_on_mclk;
vdd_dep_on_mclk   296 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h 	struct vega10_odn_clock_voltage_dependency_table vdd_dep_on_mclk;
vdd_dep_on_mclk   957 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 	pp_table_info->vdd_dep_on_mclk = NULL;
vdd_dep_on_mclk  1010 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 				&pp_table_info->vdd_dep_on_mclk,
vdd_dep_on_mclk  1054 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		pp_table_info->vdd_dep_on_mclk &&
vdd_dep_on_mclk  1055 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		pp_table_info->vdd_dep_on_mclk->count)
vdd_dep_on_mclk  1058 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 				pp_table_info->vdd_dep_on_mclk);
vdd_dep_on_mclk  1239 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 	kfree(pp_table_info->vdd_dep_on_mclk);
vdd_dep_on_mclk  1240 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 	pp_table_info->vdd_dep_on_mclk = NULL;
vdd_dep_on_mclk   524 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_mclk;
vdd_dep_on_mclk   553 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_mclk;
vdd_dep_on_mclk  1178 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		vdd_dep_table = table_info->vdd_dep_on_mclk;
vdd_dep_on_mclk  1285 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		for (i = 0; i < table_info->vdd_dep_on_mclk->count; i++) {
vdd_dep_on_mclk  1286 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 			if (mclk <= table_info->vdd_dep_on_mclk->entries[i].clk) {
vdd_dep_on_mclk  1291 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		PP_ASSERT_WITH_CODE(i < table_info->vdd_dep_on_mclk->count,
vdd_dep_on_mclk  1380 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 				table_info->vdd_dep_on_mclk,
vdd_dep_on_mclk  1654 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	count = (uint8_t)(table_info->vdd_dep_on_mclk->count);
vdd_dep_on_mclk  1656 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		if (table_info->vdd_dep_on_mclk->entries[level].clk >=
vdd_dep_on_mclk  1085 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		vdd_dep_table = table_info->vdd_dep_on_mclk;
vdd_dep_on_mclk  1184 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		for (i = 0; i < table_info->vdd_dep_on_mclk->count; i++) {
vdd_dep_on_mclk  1185 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 			if (mclk <= table_info->vdd_dep_on_mclk->entries[i].clk) {
vdd_dep_on_mclk  1190 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		PP_ASSERT_WITH_CODE(i < table_info->vdd_dep_on_mclk->count,
vdd_dep_on_mclk  1251 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 			table_info->vdd_dep_on_mclk,
vdd_dep_on_mclk  1499 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	count = (uint8_t)(table_info->vdd_dep_on_mclk->count);
vdd_dep_on_mclk  1501 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		if (table_info->vdd_dep_on_mclk->entries[level].clk >=
vdd_dep_on_mclk   980 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		vdd_dep_table = pptable_info->vdd_dep_on_mclk;
vdd_dep_on_mclk  1153 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		for (i = 0; i < table_info->vdd_dep_on_mclk->count; i++) {
vdd_dep_on_mclk  1154 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 			if (mclk <= table_info->vdd_dep_on_mclk->entries[i].clk) {
vdd_dep_on_mclk  1162 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		PP_ASSERT_WITH_CODE(i < table_info->vdd_dep_on_mclk->count,
vdd_dep_on_mclk   988 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	if (table_info->vdd_dep_on_mclk) {
vdd_dep_on_mclk   990 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 				table_info->vdd_dep_on_mclk, clock,
vdd_dep_on_mclk  1092 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		for (i = 0; i < table_info->vdd_dep_on_mclk->count; i++) {
vdd_dep_on_mclk  1093 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 			if (mclk <= table_info->vdd_dep_on_mclk->entries[i].clk) {
vdd_dep_on_mclk  1098 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		PP_ASSERT_WITH_CODE(i < table_info->vdd_dep_on_mclk->count,
vdd_dep_on_mclk  1163 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 			table_info->vdd_dep_on_mclk,
vdd_dep_on_mclk  1423 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	count = (uint8_t)(table_info->vdd_dep_on_mclk->count);
vdd_dep_on_mclk  1425 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		if (table_info->vdd_dep_on_mclk->entries[level].clk >=