vco_ctrl           67 drivers/clk/bcm/clk-cygnus.c 	.vco_ctrl = VCO_CTRL_VAL(0x18, 0x1c),
vco_ctrl          125 drivers/clk/bcm/clk-cygnus.c 	.vco_ctrl = VCO_CTRL_VAL(0x10, 0x14),
vco_ctrl          203 drivers/clk/bcm/clk-cygnus.c 	.vco_ctrl = VCO_CTRL_VAL(0x18, 0x1c),
vco_ctrl          282 drivers/clk/bcm/clk-cygnus.c 	.vco_ctrl = VCO_CTRL_VAL(0x0c, 0x10),
vco_ctrl          390 drivers/clk/bcm/clk-iproc-pll.c 	iproc_pll_write(pll, pll->control_base, ctrl->vco_ctrl.u_offset, 0);
vco_ctrl          392 drivers/clk/bcm/clk-iproc-pll.c 	val = readl(pll->control_base + ctrl->vco_ctrl.l_offset);
vco_ctrl          402 drivers/clk/bcm/clk-iproc-pll.c 	iproc_pll_write(pll, pll->control_base, ctrl->vco_ctrl.l_offset, val);
vco_ctrl          175 drivers/clk/bcm/clk-iproc.h 	struct iproc_pll_vco_ctrl vco_ctrl;
vco_ctrl           48 drivers/clk/bcm/clk-ns2.c 	.vco_ctrl = VCO_CTRL_VAL(0x10, 0xc),
vco_ctrl          111 drivers/clk/bcm/clk-ns2.c 	.vco_ctrl = VCO_CTRL_VAL(0x10, 0xc),
vco_ctrl          173 drivers/clk/bcm/clk-ns2.c 	.vco_ctrl = VCO_CTRL_VAL(0x10, 0xc),
vco_ctrl          235 drivers/clk/bcm/clk-ns2.c 	.vco_ctrl = VCO_CTRL_VAL(0x10, 0xc),
vco_ctrl           95 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c 	u32 vco_ctrl;
vco_ctrl          101 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c 	.vco_ctrl = 0x7 << 3,
vco_ctrl          756 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c 	if (clk->dvfs_params->vco_ctrl)
vco_ctrl          758 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c 		      clk->dvfs_params->vco_ctrl << GPCPLL_CFG3_VCO_CTRL_SHIFT);