vco 419 arch/powerpc/boot/4xx.c u32 cpu, plb, opb, ebc, vco; vco 446 arch/powerpc/boot/4xx.c vco = sys_clk * m; vco 447 arch/powerpc/boot/4xx.c clk_a = vco / fwdva; vco 448 arch/powerpc/boot/4xx.c clk_b = vco / fwdvb; vco 452 arch/powerpc/boot/4xx.c vco = 0; vco 749 arch/powerpc/boot/4xx.c u32 cpu, plb, opb, ebc, vco, tb, uart0, uart1; vco 774 arch/powerpc/boot/4xx.c vco = (unsigned int)(sys_clk * m); vco 778 arch/powerpc/boot/4xx.c vco = 0; vco 782 arch/powerpc/boot/4xx.c cpu = vco / (fwdva * cpudv0); vco 784 arch/powerpc/boot/4xx.c plb = vco / (fwdva * plb2xdv0 * plbdv0); vco 225 drivers/clk/analogbits/wrpll-cln28hpc.c u64 target_vco_rate, delta, best_delta, f_pre_div, vco, vco_pre; vco 279 drivers/clk/analogbits/wrpll-cln28hpc.c vco = vco_pre * f; vco 282 drivers/clk/analogbits/wrpll-cln28hpc.c if (vco > target_vco_rate) { vco 284 drivers/clk/analogbits/wrpll-cln28hpc.c vco = vco_pre * f; vco 285 drivers/clk/analogbits/wrpll-cln28hpc.c } else if (vco < MIN_VCO_FREQ) { vco 287 drivers/clk/analogbits/wrpll-cln28hpc.c vco = vco_pre * f; vco 290 drivers/clk/analogbits/wrpll-cln28hpc.c delta = abs(target_rate - vco); vco 287 drivers/clk/bcm/clk-iproc-pll.c struct iproc_pll_vco_param *vco) vco 303 drivers/clk/bcm/clk-iproc-pll.c if (ndiv_int != vco->ndiv_int) vco 309 drivers/clk/bcm/clk-iproc-pll.c if (pdiv != vco->pdiv) vco 315 drivers/clk/bcm/clk-iproc-pll.c static int pll_set_rate(struct iproc_clk *clk, struct iproc_pll_vco_param *vco, vco 321 drivers/clk/bcm/clk-iproc-pll.c unsigned long rate = vco->rate; vco 331 drivers/clk/bcm/clk-iproc-pll.c if (vco->pdiv == 0) vco 334 drivers/clk/bcm/clk-iproc-pll.c ref_freq = parent_rate / vco->pdiv; vco 364 drivers/clk/bcm/clk-iproc-pll.c if (pll_fractional_change_only(clk->pll, vco)) { vco 370 drivers/clk/bcm/clk-iproc-pll.c val |= vco->ndiv_frac << ctrl->ndiv_frac.shift; vco 407 drivers/clk/bcm/clk-iproc-pll.c val |= vco->ndiv_int << ctrl->ndiv_int.shift; vco 415 drivers/clk/bcm/clk-iproc-pll.c val |= vco->ndiv_frac << ctrl->ndiv_frac.shift; vco 423 drivers/clk/bcm/clk-iproc-pll.c val |= vco->pdiv << ctrl->pdiv.shift; vco 727 drivers/clk/bcm/clk-iproc-pll.c const struct iproc_pll_vco_param *vco, vco 794 drivers/clk/bcm/clk-iproc-pll.c if (vco) { vco 796 drivers/clk/bcm/clk-iproc-pll.c pll->vco_param = vco; vco 215 drivers/clk/bcm/clk-iproc.h const struct iproc_pll_vco_param *vco, vco 115 drivers/clk/berlin/berlin2-avpll.c struct berlin2_avpll_vco *vco = to_avpll_vco(hw); vco 118 drivers/clk/berlin/berlin2-avpll.c reg = readl_relaxed(vco->base + VCO_CTRL0); vco 119 drivers/clk/berlin/berlin2-avpll.c if (vco->flags & BERLIN2_AVPLL_BIT_QUIRK) vco 127 drivers/clk/berlin/berlin2-avpll.c struct berlin2_avpll_vco *vco = to_avpll_vco(hw); vco 130 drivers/clk/berlin/berlin2-avpll.c reg = readl_relaxed(vco->base + VCO_CTRL0); vco 131 drivers/clk/berlin/berlin2-avpll.c if (vco->flags & BERLIN2_AVPLL_BIT_QUIRK) vco 135 drivers/clk/berlin/berlin2-avpll.c writel_relaxed(reg, vco->base + VCO_CTRL0); vco 142 drivers/clk/berlin/berlin2-avpll.c struct berlin2_avpll_vco *vco = to_avpll_vco(hw); vco 145 drivers/clk/berlin/berlin2-avpll.c reg = readl_relaxed(vco->base + VCO_CTRL0); vco 146 drivers/clk/berlin/berlin2-avpll.c if (vco->flags & BERLIN2_AVPLL_BIT_QUIRK) vco 150 drivers/clk/berlin/berlin2-avpll.c writel_relaxed(reg, vco->base + VCO_CTRL0); vco 158 drivers/clk/berlin/berlin2-avpll.c struct berlin2_avpll_vco *vco = to_avpll_vco(hw); vco 163 drivers/clk/berlin/berlin2-avpll.c reg = readl_relaxed(vco->base + VCO_CTRL1); vco 184 drivers/clk/berlin/berlin2-avpll.c struct berlin2_avpll_vco *vco; vco 187 drivers/clk/berlin/berlin2-avpll.c vco = kzalloc(sizeof(*vco), GFP_KERNEL); vco 188 drivers/clk/berlin/berlin2-avpll.c if (!vco) vco 191 drivers/clk/berlin/berlin2-avpll.c vco->base = base; vco 192 drivers/clk/berlin/berlin2-avpll.c vco->flags = vco_flags; vco 193 drivers/clk/berlin/berlin2-avpll.c vco->hw.init = &init; vco 200 drivers/clk/berlin/berlin2-avpll.c return clk_hw_register(NULL, &vco->hw); vco 223 drivers/clk/clk-si544.c u64 vco; vco 248 drivers/clk/clk-si544.c vco = FVCO_MIN + ls_freq - 1; vco 249 drivers/clk/clk-si544.c do_div(vco, ls_freq); vco 250 drivers/clk/clk-si544.c settings->hs_div = vco; vco 258 drivers/clk/clk-si544.c vco = (u64)ls_freq * settings->hs_div; vco 261 drivers/clk/clk-si544.c tmp = do_div(vco, FXO); vco 262 drivers/clk/clk-si544.c settings->fb_div_int = vco; vco 265 drivers/clk/clk-si544.c vco = (u64)tmp << 32; vco 266 drivers/clk/clk-si544.c vco += FXO / 2; /* Round to nearest multiple */ vco 267 drivers/clk/clk-si544.c do_div(vco, FXO); vco 268 drivers/clk/clk-si544.c settings->fb_div_frac = vco; vco 281 drivers/clk/clk-si544.c u64 vco; vco 284 drivers/clk/clk-si544.c vco = (u64)settings->fb_div_frac * FXO; vco 285 drivers/clk/clk-si544.c vco += (FXO / 2); vco 286 drivers/clk/clk-si544.c vco >>= 32; vco 289 drivers/clk/clk-si544.c vco += (u64)settings->fb_div_int * FXO; vco 292 drivers/clk/clk-si544.c do_div(vco, d); vco 294 drivers/clk/clk-si544.c return vco; vco 798 drivers/clk/clk-stm32f4.c const struct stm32f4_vco_data *vco; vco 805 drivers/clk/clk-stm32f4.c vco = &vco_data[data->pll_num]; vco 807 drivers/clk/clk-stm32f4.c init.name = vco->vco_name; vco 815 drivers/clk/clk-stm32f4.c pll->gate.bit_idx = vco->bit_idx; vco 818 drivers/clk/clk-stm32f4.c pll->offset = vco->offset; vco 820 drivers/clk/clk-stm32f4.c pll->bit_rdy_idx = vco->bit_rdy_idx; vco 821 drivers/clk/clk-stm32f4.c pll->status = (readl(base + STM32F4_RCC_CR) >> vco->bit_idx) & 0x1; vco 835 drivers/clk/clk-stm32f4.c vco->vco_name, vco 68 drivers/clk/mediatek/clk-pll.c u64 vco; vco 76 drivers/clk/mediatek/clk-pll.c vco = (u64)fin * pcw; vco 78 drivers/clk/mediatek/clk-pll.c if (pcwfbits && (vco & GENMASK(pcwfbits - 1, 0))) vco 81 drivers/clk/mediatek/clk-pll.c vco >>= pcwfbits; vco 84 drivers/clk/mediatek/clk-pll.c vco++; vco 86 drivers/clk/mediatek/clk-pll.c return ((unsigned long)vco + postdiv - 1) / postdiv; vco 199 drivers/clk/pistachio/clk-pll.c u64 val, vco, old_postdiv1, old_postdiv2; vco 210 drivers/clk/pistachio/clk-pll.c vco = params->fref; vco 211 drivers/clk/pistachio/clk-pll.c vco *= (params->fbdiv << 24) + params->frac; vco 212 drivers/clk/pistachio/clk-pll.c vco = div64_u64(vco, params->refdiv << 24); vco 214 drivers/clk/pistachio/clk-pll.c if (vco < MIN_VCO_FRAC_FRAC || vco > MAX_VCO_FRAC_FRAC) vco 215 drivers/clk/pistachio/clk-pll.c pr_warn("%s: VCO %llu is out of range %lu..%lu\n", name, vco, vco 222 drivers/clk/pistachio/clk-pll.c if (val > vco / 16) vco 224 drivers/clk/pistachio/clk-pll.c name, val, vco / 16); vco 356 drivers/clk/pistachio/clk-pll.c u32 val, vco, old_postdiv1, old_postdiv2; vco 366 drivers/clk/pistachio/clk-pll.c vco = div_u64(params->fref * params->fbdiv, params->refdiv); vco 367 drivers/clk/pistachio/clk-pll.c if (vco < MIN_VCO_LA || vco > MAX_VCO_LA) vco 368 drivers/clk/pistachio/clk-pll.c pr_warn("%s: VCO %u is out of range %lu..%lu\n", name, vco, vco 375 drivers/clk/pistachio/clk-pll.c if (val > vco / 16) vco 377 drivers/clk/pistachio/clk-pll.c name, val, vco / 16); vco 540 drivers/clk/qcom/clk-alpha-pll.c const struct pll_vco *vco; vco 545 drivers/clk/qcom/clk-alpha-pll.c vco = alpha_pll_find_vco(pll, rate); vco 546 drivers/clk/qcom/clk-alpha-pll.c if (pll->vco_table && !vco) { vco 561 drivers/clk/qcom/clk-alpha-pll.c if (vco) { vco 564 drivers/clk/qcom/clk-alpha-pll.c vco->val << PLL_VCO_SHIFT); vco 1215 drivers/clk/qcom/gcc-ipq4019.c u64 vco; vco 1223 drivers/clk/qcom/gcc-ipq4019.c vco = parent_rate / refclkdiv; vco 1224 drivers/clk/qcom/gcc-ipq4019.c vco *= 2; vco 1225 drivers/clk/qcom/gcc-ipq4019.c vco *= fdbkdiv; vco 1227 drivers/clk/qcom/gcc-ipq4019.c return vco; vco 97 drivers/clk/spear/clk-vco-pll.c for (*index = 0; *index < pll->vco->rtbl_cnt; (*index)++) { vco 100 drivers/clk/spear/clk-vco-pll.c *prate = pll_calc_rate(pll->vco->rtbl, vco_parent_rate, *index, vco 131 drivers/clk/spear/clk-vco-pll.c if (pll->vco->lock) vco 132 drivers/clk/spear/clk-vco-pll.c spin_lock_irqsave(pll->vco->lock, flags); vco 134 drivers/clk/spear/clk-vco-pll.c p = readl_relaxed(pll->vco->cfg_reg); vco 136 drivers/clk/spear/clk-vco-pll.c if (pll->vco->lock) vco 137 drivers/clk/spear/clk-vco-pll.c spin_unlock_irqrestore(pll->vco->lock, flags); vco 148 drivers/clk/spear/clk-vco-pll.c struct pll_rate_tbl *rtbl = pll->vco->rtbl; vco 154 drivers/clk/spear/clk-vco-pll.c if (pll->vco->lock) vco 155 drivers/clk/spear/clk-vco-pll.c spin_lock_irqsave(pll->vco->lock, flags); vco 157 drivers/clk/spear/clk-vco-pll.c val = readl_relaxed(pll->vco->cfg_reg); vco 160 drivers/clk/spear/clk-vco-pll.c writel_relaxed(val, pll->vco->cfg_reg); vco 162 drivers/clk/spear/clk-vco-pll.c if (pll->vco->lock) vco 163 drivers/clk/spear/clk-vco-pll.c spin_unlock_irqrestore(pll->vco->lock, flags); vco 177 drivers/clk/spear/clk-vco-pll.c struct clk_vco *vco = to_clk_vco(hw); vco 179 drivers/clk/spear/clk-vco-pll.c return pll_calc_rate(vco->rtbl, prate, index, NULL); vco 185 drivers/clk/spear/clk-vco-pll.c struct clk_vco *vco = to_clk_vco(hw); vco 189 drivers/clk/spear/clk-vco-pll.c vco->rtbl_cnt, &unused); vco 195 drivers/clk/spear/clk-vco-pll.c struct clk_vco *vco = to_clk_vco(hw); vco 199 drivers/clk/spear/clk-vco-pll.c if (vco->lock) vco 200 drivers/clk/spear/clk-vco-pll.c spin_lock_irqsave(vco->lock, flags); vco 202 drivers/clk/spear/clk-vco-pll.c mode = (readl_relaxed(vco->mode_reg) >> PLL_MODE_SHIFT) & PLL_MODE_MASK; vco 204 drivers/clk/spear/clk-vco-pll.c val = readl_relaxed(vco->cfg_reg); vco 206 drivers/clk/spear/clk-vco-pll.c if (vco->lock) vco 207 drivers/clk/spear/clk-vco-pll.c spin_unlock_irqrestore(vco->lock, flags); vco 233 drivers/clk/spear/clk-vco-pll.c struct clk_vco *vco = to_clk_vco(hw); vco 234 drivers/clk/spear/clk-vco-pll.c struct pll_rate_tbl *rtbl = vco->rtbl; vco 238 drivers/clk/spear/clk-vco-pll.c clk_round_rate_index(hw, drate, prate, vco_calc_rate, vco->rtbl_cnt, vco 241 drivers/clk/spear/clk-vco-pll.c if (vco->lock) vco 242 drivers/clk/spear/clk-vco-pll.c spin_lock_irqsave(vco->lock, flags); vco 244 drivers/clk/spear/clk-vco-pll.c val = readl_relaxed(vco->mode_reg); vco 247 drivers/clk/spear/clk-vco-pll.c writel_relaxed(val, vco->mode_reg); vco 249 drivers/clk/spear/clk-vco-pll.c val = readl_relaxed(vco->cfg_reg); vco 261 drivers/clk/spear/clk-vco-pll.c writel_relaxed(val, vco->cfg_reg); vco 263 drivers/clk/spear/clk-vco-pll.c if (vco->lock) vco 264 drivers/clk/spear/clk-vco-pll.c spin_unlock_irqrestore(vco->lock, flags); vco 282 drivers/clk/spear/clk-vco-pll.c struct clk_vco *vco; vco 294 drivers/clk/spear/clk-vco-pll.c vco = kzalloc(sizeof(*vco), GFP_KERNEL); vco 295 drivers/clk/spear/clk-vco-pll.c if (!vco) vco 303 drivers/clk/spear/clk-vco-pll.c vco->mode_reg = mode_reg; vco 304 drivers/clk/spear/clk-vco-pll.c vco->cfg_reg = cfg_reg; vco 305 drivers/clk/spear/clk-vco-pll.c vco->rtbl = rtbl; vco 306 drivers/clk/spear/clk-vco-pll.c vco->rtbl_cnt = rtbl_cnt; vco 307 drivers/clk/spear/clk-vco-pll.c vco->lock = lock; vco 308 drivers/clk/spear/clk-vco-pll.c vco->hw.init = &vco_init; vco 310 drivers/clk/spear/clk-vco-pll.c pll->vco = vco; vco 338 drivers/clk/spear/clk-vco-pll.c vco_clk = clk_register(NULL, &vco->hw); vco 354 drivers/clk/spear/clk-vco-pll.c kfree(vco); vco 104 drivers/clk/spear/clk.h struct clk_vco *vco; vco 74 drivers/clk/versatile/clk-icst.c static int vco_get(struct clk_icst *icst, struct icst_vco *vco) vco 92 drivers/clk/versatile/clk-icst.c vco->v = val & INTEGRATOR_AP_CM_BITS; vco 93 drivers/clk/versatile/clk-icst.c vco->r = 22; vco 94 drivers/clk/versatile/clk-icst.c vco->s = 1; vco 107 drivers/clk/versatile/clk-icst.c vco->v = val & INTEGRATOR_AP_SYS_BITS; vco 108 drivers/clk/versatile/clk-icst.c vco->r = 46; vco 109 drivers/clk/versatile/clk-icst.c vco->s = 3; vco 124 drivers/clk/versatile/clk-icst.c vco->v = divxy ? 17 : 14; vco 125 drivers/clk/versatile/clk-icst.c vco->r = divxy ? 22 : 14; vco 126 drivers/clk/versatile/clk-icst.c vco->s = 1; vco 139 drivers/clk/versatile/clk-icst.c vco->v = val & 0xFF; vco 140 drivers/clk/versatile/clk-icst.c vco->r = 22; vco 141 drivers/clk/versatile/clk-icst.c vco->s = (val >> 8) & 7; vco 146 drivers/clk/versatile/clk-icst.c vco->v = (val >> 12) & 0xFF; vco 147 drivers/clk/versatile/clk-icst.c vco->r = 22; vco 148 drivers/clk/versatile/clk-icst.c vco->s = (val >> 20) & 7; vco 152 drivers/clk/versatile/clk-icst.c vco->v = val & 0x1ff; vco 153 drivers/clk/versatile/clk-icst.c vco->r = (val >> 9) & 0x7f; vco 154 drivers/clk/versatile/clk-icst.c vco->s = (val >> 16) & 03; vco 163 drivers/clk/versatile/clk-icst.c static int vco_set(struct clk_icst *icst, struct icst_vco vco) vco 173 drivers/clk/versatile/clk-icst.c val = vco.v & 0xFF; vco 174 drivers/clk/versatile/clk-icst.c if (vco.v & 0x100) vco 176 drivers/clk/versatile/clk-icst.c if (vco.s != 1) vco 178 drivers/clk/versatile/clk-icst.c if (vco.r != 22) vco 183 drivers/clk/versatile/clk-icst.c val = vco.v & 0xFF; vco 184 drivers/clk/versatile/clk-icst.c if (vco.v & 0x100) vco 186 drivers/clk/versatile/clk-icst.c if (vco.s != 3) vco 188 drivers/clk/versatile/clk-icst.c if (vco.r != 46) vco 193 drivers/clk/versatile/clk-icst.c val = (vco.v & 0xFF) | vco.s << 8; vco 194 drivers/clk/versatile/clk-icst.c if (vco.v & 0x100) vco 196 drivers/clk/versatile/clk-icst.c if (vco.r != 22) vco 201 drivers/clk/versatile/clk-icst.c val = ((vco.v & 0xFF) << 12) | (vco.s << 20); vco 202 drivers/clk/versatile/clk-icst.c if (vco.v & 0x100) vco 204 drivers/clk/versatile/clk-icst.c if (vco.r != 22) vco 210 drivers/clk/versatile/clk-icst.c val = vco.v | (vco.r << 9) | (vco.s << 16); vco 234 drivers/clk/versatile/clk-icst.c struct icst_vco vco; vco 239 drivers/clk/versatile/clk-icst.c ret = vco_get(icst, &vco); vco 244 drivers/clk/versatile/clk-icst.c icst->rate = icst_hz(icst->params, vco); vco 252 drivers/clk/versatile/clk-icst.c struct icst_vco vco; vco 294 drivers/clk/versatile/clk-icst.c vco = icst_hz_to_vco(icst->params, rate); vco 295 drivers/clk/versatile/clk-icst.c return icst_hz(icst->params, vco); vco 302 drivers/clk/versatile/clk-icst.c struct icst_vco vco; vco 336 drivers/clk/versatile/clk-icst.c vco = icst_hz_to_vco(icst->params, rate); vco 337 drivers/clk/versatile/clk-icst.c icst->rate = icst_hz(icst->params, vco); vco 338 drivers/clk/versatile/clk-icst.c return vco_set(icst, vco); vco 27 drivers/clk/versatile/icst.c unsigned long icst_hz(const struct icst_params *p, struct icst_vco vco) vco 29 drivers/clk/versatile/icst.c u64 dividend = p->ref * 2 * (u64)(vco.v + 8); vco 30 drivers/clk/versatile/icst.c u32 divisor = (vco.r + 2) * p->s2div[vco.s]; vco 49 drivers/clk/versatile/icst.c struct icst_vco vco = { .s = 1, .v = p->vd_max, .r = p->rd_max }; vco 66 drivers/clk/versatile/icst.c return vco; vco 68 drivers/clk/versatile/icst.c vco.s = p->idx2s[i]; vco 91 drivers/clk/versatile/icst.c vco.v = vd - 8; vco 92 drivers/clk/versatile/icst.c vco.r = rd - 2; vco 99 drivers/clk/versatile/icst.c return vco; vco 30 drivers/clk/versatile/icst.h unsigned long icst_hz(const struct icst_params *p, struct icst_vco vco); vco 37 drivers/gpu/drm/gma500/cdv_intel_display.c .vco = {.min = 1800000, .max = 3600000}, vco 49 drivers/gpu/drm/gma500/cdv_intel_display.c .vco = {.min = 1800000, .max = 3600000}, vco 64 drivers/gpu/drm/gma500/cdv_intel_display.c .vco = {.min = 1809000, .max = 3564000}, vco 76 drivers/gpu/drm/gma500/cdv_intel_display.c .vco = {.min = 1800000, .max = 3600000}, vco 88 drivers/gpu/drm/gma500/cdv_intel_display.c .vco = {.min = 1809000, .max = 3564000}, vco 100 drivers/gpu/drm/gma500/cdv_intel_display.c .vco = {.min = 1800000, .max = 3600000}, vco 289 drivers/gpu/drm/gma500/cdv_intel_display.c if (clock->vco < 2250000) { vco 292 drivers/gpu/drm/gma500/cdv_intel_display.c } else if (clock->vco < 2750000) { vco 295 drivers/gpu/drm/gma500/cdv_intel_display.c } else if (clock->vco < 3300000) { vco 396 drivers/gpu/drm/gma500/cdv_intel_display.c clock->vco = (refclk * clock->m) / clock->n; vco 397 drivers/gpu/drm/gma500/cdv_intel_display.c clock->dot = clock->vco / clock->p; vco 834 drivers/gpu/drm/gma500/cdv_intel_display.c clock->vco = refclk * clock->m / (clock->n + 2); vco 835 drivers/gpu/drm/gma500/cdv_intel_display.c clock->dot = clock->vco / clock->p; vco 687 drivers/gpu/drm/gma500/gma_display.c if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) vco 25 drivers/gpu/drm/gma500/gma_display.h int vco; vco 40 drivers/gpu/drm/gma500/gma_display.h struct gma_range_t dot, vco, n, m, m1, m2, p, p1; vco 64 drivers/gpu/drm/gma500/oaktrail_crtc.c .vco = {.min = 1400000, .max = 2800000}, vco 144 drivers/gpu/drm/gma500/oaktrail_crtc.c if (target_vco > limit->vco.max) vco 147 drivers/gpu/drm/gma500/oaktrail_crtc.c if (target_vco < limit->vco.min) vco 104 drivers/gpu/drm/gma500/oaktrail_hdmi.c struct intel_range vco, np, nr, nf; vco 124 drivers/gpu/drm/gma500/oaktrail_hdmi.c .vco = { .min = VCO_MIN, .max = VCO_MAX }, vco 182 drivers/gpu/drm/gma500/oaktrail_hdmi.c np_min = DIV_ROUND_UP(oaktrail_hdmi_limit.vco.min, target * 10); vco 183 drivers/gpu/drm/gma500/oaktrail_hdmi.c np_max = oaktrail_hdmi_limit.vco.max / (target * 10); vco 27 drivers/gpu/drm/gma500/psb_intel_display.c .vco = {.min = 1400000, .max = 2800000}, vco 39 drivers/gpu/drm/gma500/psb_intel_display.c .vco = {.min = 1400000, .max = 2800000}, vco 70 drivers/gpu/drm/gma500/psb_intel_display.c clock->vco = refclk * clock->m / (clock->n + 2); vco 71 drivers/gpu/drm/gma500/psb_intel_display.c clock->dot = clock->vco / clock->p; vco 222 drivers/gpu/drm/i915/display/intel_cdclk.c unsigned int vco; vco 242 drivers/gpu/drm/i915/display/intel_cdclk.c vco = vco_table[tmp & 0x7]; vco 243 drivers/gpu/drm/i915/display/intel_cdclk.c if (vco == 0) vco 246 drivers/gpu/drm/i915/display/intel_cdclk.c DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco); vco 248 drivers/gpu/drm/i915/display/intel_cdclk.c return vco; vco 263 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->vco = intel_hpll_vco(dev_priv); vco 272 drivers/gpu/drm/i915/display/intel_cdclk.c switch (cdclk_state->vco) { vco 289 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, vco 295 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->vco, tmp); vco 343 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->vco = intel_hpll_vco(dev_priv); vco 352 drivers/gpu/drm/i915/display/intel_cdclk.c switch (cdclk_state->vco) { vco 366 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, vco 372 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->vco, tmp); vco 383 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->vco = intel_hpll_vco(dev_priv); vco 389 drivers/gpu/drm/i915/display/intel_cdclk.c switch (cdclk_state->vco) { vco 400 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->vco, tmp); vco 471 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->vco = vlv_get_hpll_vco(dev_priv); vco 474 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->vco); vco 787 drivers/gpu/drm/i915/display/intel_cdclk.c static int skl_calc_cdclk(int min_cdclk, int vco) vco 789 drivers/gpu/drm/i915/display/intel_cdclk.c if (vco == 8640000) { vco 828 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->vco = 0; vco 850 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->vco = 8100000; vco 854 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->vco = 8640000; vco 871 drivers/gpu/drm/i915/display/intel_cdclk.c if (cdclk_state->vco == 0) vco 876 drivers/gpu/drm/i915/display/intel_cdclk.c if (cdclk_state->vco == 8640000) { vco 930 drivers/gpu/drm/i915/display/intel_cdclk.c int vco) vco 932 drivers/gpu/drm/i915/display/intel_cdclk.c bool changed = dev_priv->skl_preferred_vco_freq != vco; vco 934 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->skl_preferred_vco_freq = vco; vco 940 drivers/gpu/drm/i915/display/intel_cdclk.c static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco) vco 944 drivers/gpu/drm/i915/display/intel_cdclk.c WARN_ON(vco != 8100000 && vco != 8640000); vco 960 drivers/gpu/drm/i915/display/intel_cdclk.c if (vco == 8640000) vco 975 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->cdclk.hw.vco = vco; vco 978 drivers/gpu/drm/i915/display/intel_cdclk.c skl_set_preferred_cdclk_vco(dev_priv, vco); vco 987 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->cdclk.hw.vco = 0; vco 995 drivers/gpu/drm/i915/display/intel_cdclk.c int vco = cdclk_state->vco; vco 1007 drivers/gpu/drm/i915/display/intel_cdclk.c WARN_ON_ONCE(IS_SKYLAKE(dev_priv) && vco == 8640000); vco 1023 drivers/gpu/drm/i915/display/intel_cdclk.c WARN_ON(vco != 0); vco 1042 drivers/gpu/drm/i915/display/intel_cdclk.c if (dev_priv->cdclk.hw.vco != 0 && vco 1043 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->cdclk.hw.vco != vco) vco 1048 drivers/gpu/drm/i915/display/intel_cdclk.c if (dev_priv->cdclk.hw.vco != vco) { vco 1060 drivers/gpu/drm/i915/display/intel_cdclk.c if (dev_priv->cdclk.hw.vco != vco) vco 1061 drivers/gpu/drm/i915/display/intel_cdclk.c skl_dpll0_enable(dev_priv, vco); vco 1098 drivers/gpu/drm/i915/display/intel_cdclk.c if (dev_priv->cdclk.hw.vco == 0 || vco 1121 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->cdclk.hw.vco = -1; vco 1131 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->cdclk.hw.vco != 0) { vco 1138 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->cdclk.hw.vco); vco 1144 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state.vco = dev_priv->skl_preferred_vco_freq; vco 1145 drivers/gpu/drm/i915/display/intel_cdclk.c if (cdclk_state.vco == 0) vco 1146 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state.vco = 8100000; vco 1147 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state.cdclk = skl_calc_cdclk(0, cdclk_state.vco); vco 1158 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state.vco = 0; vco 1245 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->vco = 0; vco 1255 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->vco = (val & BXT_DE_PLL_RATIO_MASK) * cdclk_state->ref; vco 1268 drivers/gpu/drm/i915/display/intel_cdclk.c if (cdclk_state->vco == 0) vco 1292 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, div); vco 1312 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->cdclk.hw.vco = 0; vco 1315 drivers/gpu/drm/i915/display/intel_cdclk.c static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco) vco 1317 drivers/gpu/drm/i915/display/intel_cdclk.c int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref); vco 1332 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->cdclk.hw.vco = vco; vco 1340 drivers/gpu/drm/i915/display/intel_cdclk.c int vco = cdclk_state->vco; vco 1345 drivers/gpu/drm/i915/display/intel_cdclk.c switch (DIV_ROUND_CLOSEST(vco, cdclk)) { vco 1348 drivers/gpu/drm/i915/display/intel_cdclk.c WARN_ON(vco != 0); vco 1379 drivers/gpu/drm/i915/display/intel_cdclk.c if (dev_priv->cdclk.hw.vco != 0 && vco 1380 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->cdclk.hw.vco != vco) vco 1383 drivers/gpu/drm/i915/display/intel_cdclk.c if (dev_priv->cdclk.hw.vco != vco) vco 1384 drivers/gpu/drm/i915/display/intel_cdclk.c bxt_de_pll_enable(dev_priv, vco); vco 1427 drivers/gpu/drm/i915/display/intel_cdclk.c if (dev_priv->cdclk.hw.vco == 0 || vco 1465 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->cdclk.hw.vco = -1; vco 1475 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->cdclk.hw.vco != 0) vco 1487 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state.vco = glk_de_pll_vco(dev_priv, cdclk_state.cdclk); vco 1490 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state.vco = bxt_de_pll_vco(dev_priv, cdclk_state.cdclk); vco 1502 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state.vco = 0; vco 1538 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->vco = 0; vco 1547 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->vco = (val & CNL_CDCLK_PLL_RATIO_MASK) * cdclk_state->ref; vco 1560 drivers/gpu/drm/i915/display/intel_cdclk.c if (cdclk_state->vco == 0) vco 1577 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, div); vco 1600 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->cdclk.hw.vco = 0; vco 1603 drivers/gpu/drm/i915/display/intel_cdclk.c static void cnl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco) vco 1605 drivers/gpu/drm/i915/display/intel_cdclk.c int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref); vco 1618 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->cdclk.hw.vco = vco; vco 1626 drivers/gpu/drm/i915/display/intel_cdclk.c int vco = cdclk_state->vco; vco 1641 drivers/gpu/drm/i915/display/intel_cdclk.c switch (DIV_ROUND_CLOSEST(vco, cdclk)) { vco 1644 drivers/gpu/drm/i915/display/intel_cdclk.c WARN_ON(vco != 0); vco 1654 drivers/gpu/drm/i915/display/intel_cdclk.c if (dev_priv->cdclk.hw.vco != 0 && vco 1655 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->cdclk.hw.vco != vco) vco 1658 drivers/gpu/drm/i915/display/intel_cdclk.c if (dev_priv->cdclk.hw.vco != vco) vco 1659 drivers/gpu/drm/i915/display/intel_cdclk.c cnl_cdclk_pll_enable(dev_priv, vco); vco 1714 drivers/gpu/drm/i915/display/intel_cdclk.c if (dev_priv->cdclk.hw.vco == 0 || vco 1746 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->cdclk.hw.vco = -1; vco 1821 drivers/gpu/drm/i915/display/intel_cdclk.c unsigned int vco = cdclk_state->vco; vco 1834 drivers/gpu/drm/i915/display/intel_cdclk.c if (dev_priv->cdclk.hw.vco != 0 && vco 1835 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->cdclk.hw.vco != vco) vco 1838 drivers/gpu/drm/i915/display/intel_cdclk.c if (dev_priv->cdclk.hw.vco != vco) vco 1839 drivers/gpu/drm/i915/display/intel_cdclk.c cnl_cdclk_pll_enable(dev_priv, vco); vco 1910 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->vco = 0; vco 1915 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->vco = (val & BXT_DE_PLL_RATIO_MASK) * cdclk_state->ref; vco 1920 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->cdclk = cdclk_state->vco / 2; vco 1960 drivers/gpu/drm/i915/display/intel_cdclk.c sanitized_state.vco = icl_calc_cdclk_pll_vco(dev_priv, vco 1974 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state.vco = 0; vco 1988 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->cdclk.hw.vco != 0) vco 1994 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state.vco = cnl_cdclk_pll_vco(dev_priv, cdclk_state.cdclk); vco 2005 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state.vco = 0; vco 2063 drivers/gpu/drm/i915/display/intel_cdclk.c a->vco != b->vco || vco 2085 drivers/gpu/drm/i915/display/intel_cdclk.c a->vco == b->vco && vco 2128 drivers/gpu/drm/i915/display/intel_cdclk.c context, cdclk_state->cdclk, cdclk_state->vco, vco 2421 drivers/gpu/drm/i915/display/intel_cdclk.c int vco, i; vco 2423 drivers/gpu/drm/i915/display/intel_cdclk.c vco = state->cdclk.logical.vco; vco 2424 drivers/gpu/drm/i915/display/intel_cdclk.c if (!vco) vco 2425 drivers/gpu/drm/i915/display/intel_cdclk.c vco = dev_priv->skl_preferred_vco_freq; vco 2441 drivers/gpu/drm/i915/display/intel_cdclk.c vco = 8640000; vco 2444 drivers/gpu/drm/i915/display/intel_cdclk.c vco = 8100000; vco 2449 drivers/gpu/drm/i915/display/intel_cdclk.c return vco; vco 2454 drivers/gpu/drm/i915/display/intel_cdclk.c int min_cdclk, cdclk, vco; vco 2460 drivers/gpu/drm/i915/display/intel_cdclk.c vco = skl_dpll0_vco(state); vco 2466 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk = skl_calc_cdclk(min_cdclk, vco); vco 2468 drivers/gpu/drm/i915/display/intel_cdclk.c state->cdclk.logical.vco = vco; vco 2474 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk = skl_calc_cdclk(state->cdclk.force_min_cdclk, vco); vco 2476 drivers/gpu/drm/i915/display/intel_cdclk.c state->cdclk.actual.vco = vco; vco 2490 drivers/gpu/drm/i915/display/intel_cdclk.c int min_cdclk, cdclk, vco; vco 2498 drivers/gpu/drm/i915/display/intel_cdclk.c vco = glk_de_pll_vco(dev_priv, cdclk); vco 2501 drivers/gpu/drm/i915/display/intel_cdclk.c vco = bxt_de_pll_vco(dev_priv, cdclk); vco 2504 drivers/gpu/drm/i915/display/intel_cdclk.c state->cdclk.logical.vco = vco; vco 2512 drivers/gpu/drm/i915/display/intel_cdclk.c vco = glk_de_pll_vco(dev_priv, cdclk); vco 2515 drivers/gpu/drm/i915/display/intel_cdclk.c vco = bxt_de_pll_vco(dev_priv, cdclk); vco 2518 drivers/gpu/drm/i915/display/intel_cdclk.c state->cdclk.actual.vco = vco; vco 2532 drivers/gpu/drm/i915/display/intel_cdclk.c int min_cdclk, cdclk, vco; vco 2539 drivers/gpu/drm/i915/display/intel_cdclk.c vco = cnl_cdclk_pll_vco(dev_priv, cdclk); vco 2541 drivers/gpu/drm/i915/display/intel_cdclk.c state->cdclk.logical.vco = vco; vco 2549 drivers/gpu/drm/i915/display/intel_cdclk.c vco = cnl_cdclk_pll_vco(dev_priv, cdclk); vco 2551 drivers/gpu/drm/i915/display/intel_cdclk.c state->cdclk.actual.vco = vco; vco 2566 drivers/gpu/drm/i915/display/intel_cdclk.c int min_cdclk, cdclk, vco; vco 2573 drivers/gpu/drm/i915/display/intel_cdclk.c vco = icl_calc_cdclk_pll_vco(dev_priv, cdclk); vco 2575 drivers/gpu/drm/i915/display/intel_cdclk.c state->cdclk.logical.vco = vco; vco 2583 drivers/gpu/drm/i915/display/intel_cdclk.c vco = icl_calc_cdclk_pll_vco(dev_priv, cdclk); vco 2585 drivers/gpu/drm/i915/display/intel_cdclk.c state->cdclk.actual.vco = vco; vco 2637 drivers/gpu/drm/i915/display/intel_cdclk.c int max_cdclk, vco; vco 2639 drivers/gpu/drm/i915/display/intel_cdclk.c vco = dev_priv->skl_preferred_vco_freq; vco 2640 drivers/gpu/drm/i915/display/intel_cdclk.c WARN_ON(vco != 8100000 && vco != 8640000); vco 2656 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco); vco 152 drivers/gpu/drm/i915/display/intel_display.c } dot, vco, n, m, m1, m2, p, p1; vco 228 drivers/gpu/drm/i915/display/intel_display.c .vco = { .min = 908000, .max = 1512000 }, vco 241 drivers/gpu/drm/i915/display/intel_display.c .vco = { .min = 908000, .max = 1512000 }, vco 254 drivers/gpu/drm/i915/display/intel_display.c .vco = { .min = 908000, .max = 1512000 }, vco 267 drivers/gpu/drm/i915/display/intel_display.c .vco = { .min = 1400000, .max = 2800000 }, vco 280 drivers/gpu/drm/i915/display/intel_display.c .vco = { .min = 1400000, .max = 2800000 }, vco 294 drivers/gpu/drm/i915/display/intel_display.c .vco = { .min = 1750000, .max = 3500000}, vco 309 drivers/gpu/drm/i915/display/intel_display.c .vco = { .min = 1750000, .max = 3500000}, vco 322 drivers/gpu/drm/i915/display/intel_display.c .vco = { .min = 1750000, .max = 3500000 }, vco 336 drivers/gpu/drm/i915/display/intel_display.c .vco = { .min = 1750000, .max = 3500000 }, vco 350 drivers/gpu/drm/i915/display/intel_display.c .vco = { .min = 1700000, .max = 3500000 }, vco 365 drivers/gpu/drm/i915/display/intel_display.c .vco = { .min = 1700000, .max = 3500000 }, vco 383 drivers/gpu/drm/i915/display/intel_display.c .vco = { .min = 1760000, .max = 3510000 }, vco 396 drivers/gpu/drm/i915/display/intel_display.c .vco = { .min = 1760000, .max = 3510000 }, vco 409 drivers/gpu/drm/i915/display/intel_display.c .vco = { .min = 1760000, .max = 3510000 }, vco 423 drivers/gpu/drm/i915/display/intel_display.c .vco = { .min = 1760000, .max = 3510000 }, vco 436 drivers/gpu/drm/i915/display/intel_display.c .vco = { .min = 1760000, .max = 3510000 }, vco 455 drivers/gpu/drm/i915/display/intel_display.c .vco = { .min = 4000000, .max = 6000000 }, vco 471 drivers/gpu/drm/i915/display/intel_display.c .vco = { .min = 4800000, .max = 6480000 }, vco 482 drivers/gpu/drm/i915/display/intel_display.c .vco = { .min = 4800000, .max = 6700000 }, vco 539 drivers/gpu/drm/i915/display/intel_display.c clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); vco 540 drivers/gpu/drm/i915/display/intel_display.c clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); vco 556 drivers/gpu/drm/i915/display/intel_display.c clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); vco 557 drivers/gpu/drm/i915/display/intel_display.c clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); vco 568 drivers/gpu/drm/i915/display/intel_display.c clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); vco 569 drivers/gpu/drm/i915/display/intel_display.c clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); vco 580 drivers/gpu/drm/i915/display/intel_display.c clock->vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock->m), vco 582 drivers/gpu/drm/i915/display/intel_display.c clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); vco 619 drivers/gpu/drm/i915/display/intel_display.c if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) vco 7847 drivers/gpu/drm/i915/display/intel_display.c int vco; vco 7863 drivers/gpu/drm/i915/display/intel_display.c vco = pipe_config->dpll.vco; vco 7905 drivers/gpu/drm/i915/display/intel_display.c if (vco == 5400000) { vco 7910 drivers/gpu/drm/i915/display/intel_display.c } else if (vco <= 6200000) { vco 7915 drivers/gpu/drm/i915/display/intel_display.c } else if (vco <= 6480000) { vco 16302 drivers/gpu/drm/i915/display/intel_display.c pipe_name(pipe), clock.vco, clock.dot); vco 444 drivers/gpu/drm/i915/display/intel_display_types.h int vco; vco 1734 drivers/gpu/drm/i915/display/intel_dpll_mgr.c int vco; vco 1775 drivers/gpu/drm/i915/display/intel_dpll_mgr.c clk_div->vco = best_clock.vco; vco 1794 drivers/gpu/drm/i915/display/intel_dpll_mgr.c clk_div->vco = clock * 10 / 2 * clk_div->p1 * clk_div->p2; vco 1802 drivers/gpu/drm/i915/display/intel_dpll_mgr.c int vco = clk_div->vco; vco 1808 drivers/gpu/drm/i915/display/intel_dpll_mgr.c if (vco >= 6200000 && vco <= 6700000) { vco 1813 drivers/gpu/drm/i915/display/intel_dpll_mgr.c } else if ((vco > 5400000 && vco < 6200000) || vco 1814 drivers/gpu/drm/i915/display/intel_dpll_mgr.c (vco >= 4800000 && vco < 5400000)) { vco 1819 drivers/gpu/drm/i915/display/intel_dpll_mgr.c } else if (vco == 5400000) { vco 1278 drivers/gpu/drm/i915/i915_drv.h unsigned int cdclk, vco, ref, bypass; vco 629 drivers/gpu/drm/mgag200/mgag200_mode.c unsigned int computed, vco; vco 650 drivers/gpu/drm/mgag200/mgag200_mode.c vco = pllreffreq * (testn + 1) / vco 652 drivers/gpu/drm/mgag200/mgag200_mode.c if (vco < vcomin) vco 654 drivers/gpu/drm/mgag200/mgag200_mode.c if (vco > vcomax) vco 656 drivers/gpu/drm/mgag200/mgag200_mode.c computed = vco / (m_div_val[testm] * (testo + 1)); vco 172 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c u64 vco, vco_optimal; vco 185 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c vco = bclk >> half_rate_mode; vco 186 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c vco *= ratio_mult; vco 187 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c vco_freq[vco_freq_index++] = vco; vco 445 drivers/gpu/drm/radeon/cypress_dpm.c u32 vco = clkf * ref_clk; vco 449 drivers/gpu/drm/radeon/cypress_dpm.c if (vco > 500000) vco 451 drivers/gpu/drm/radeon/cypress_dpm.c if (vco > 400000) vco 453 drivers/gpu/drm/radeon/cypress_dpm.c if (vco > 330000) vco 455 drivers/gpu/drm/radeon/cypress_dpm.c if (vco > 250000) vco 457 drivers/gpu/drm/radeon/cypress_dpm.c if (vco > 160000) vco 459 drivers/gpu/drm/radeon/cypress_dpm.c if (vco > 120000) vco 465 drivers/gpu/drm/radeon/cypress_dpm.c if (vco > 250000) vco 467 drivers/gpu/drm/radeon/cypress_dpm.c if (vco > 200000) vco 469 drivers/gpu/drm/radeon/cypress_dpm.c if (vco > 150000) vco 1199 drivers/gpu/drm/radeon/radeon_display.c uint32_t vco; vco 1208 drivers/gpu/drm/radeon/radeon_display.c vco = radeon_div(tmp, ref_div); vco 1210 drivers/gpu/drm/radeon/radeon_display.c if (vco < pll_out_min) { vco 1213 drivers/gpu/drm/radeon/radeon_display.c } else if (vco > pll_out_max) { vco 1231 drivers/gpu/drm/radeon/radeon_display.c vco_diff = abs(vco - best_vco); vco 360 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c int ret, i, vco; vco 374 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c vco = (dsi->lane_mbps < 200) ? 0 : (dsi->lane_mbps + 100) / 200; vco 392 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c VCO_RANGE_CON_SEL(vco) | vco 207 drivers/iio/frequency/adf4371.c static void adf4371_pll_fract_n_compute(unsigned long long vco, vco 217 drivers/iio/frequency/adf4371.c tmp = do_div(vco, pfd); vco 221 drivers/iio/frequency/adf4371.c *integer = vco; vco 1237 drivers/media/dvb-frontends/cx24120.c u32 nxtal_khz, vco; vco 1242 drivers/media/dvb-frontends/cx24120.c vco = nxtal_khz * 10; vco 1243 drivers/media/dvb-frontends/cx24120.c inv_vco = DIV_ROUND_CLOSEST_ULL(0x400000000ULL, vco); vco 1246 drivers/media/dvb-frontends/cx24120.c xtal_khz, vco, inv_vco); vco 1250 drivers/media/dvb-frontends/cx24120.c cmd.arg[0] = (vco >> 16) & 0xff; vco 1251 drivers/media/dvb-frontends/cx24120.c cmd.arg[1] = (vco >> 8) & 0xff; vco 1252 drivers/media/dvb-frontends/cx24120.c cmd.arg[2] = vco & 0xff; vco 278 drivers/media/i2c/mt9t112.c u32 vco, clk; vco 307 drivers/media/i2c/mt9t112.c vco = 2 * m * ext / (n + 1); vco 308 drivers/media/i2c/mt9t112.c enable = ((vco < 384000) || (vco > 768000)) ? "X" : ""; vco 309 drivers/media/i2c/mt9t112.c dev_dbg(&client->dev, "VCO : %10u K %s\n", vco, enable); vco 311 drivers/media/i2c/mt9t112.c clk = vco / (p1 + 1) / (p2 + 1); vco 315 drivers/media/i2c/mt9t112.c clk = vco / (p3 + 1); vco 319 drivers/media/i2c/mt9t112.c clk = vco / (p6 + 1); vco 323 drivers/media/i2c/mt9t112.c clk = vco / (p5 + 1); vco 327 drivers/media/i2c/mt9t112.c clk = vco / (p4 + 1); vco 331 drivers/media/i2c/mt9t112.c clk = vco / (p7 + 1); vco 224 drivers/media/tuners/max2165.c u8 vco, vco_sub_band, adc; vco 236 drivers/media/tuners/max2165.c vco = autotune >> 6; vco 246 drivers/media/tuners/max2165.c dprintk("VCO: %d, VCO Sub-band: %d, ADC: %d\n", vco, vco_sub_band, adc); vco 571 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c u64 vco; vco 577 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c vco = parent_rate * nf; vco 580 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c do_div(vco, nd * 5); vco 590 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c do_div(vco, (nd * (no_a == 1 ? no_b : no_a) * no_d * 2)); vco 593 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c inno->pixclock = vco; vco 597 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c return vco; vco 718 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c u64 vco; vco 724 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c vco = parent_rate * nf; vco 730 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c vco += DIV_ROUND_CLOSEST(parent_rate * frac, (1 << 24)); vco 734 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c do_div(vco, nd * 5); vco 745 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c do_div(vco, (nd * (no_a == 1 ? no_b : no_a) * no_d * 2)); vco 748 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c inno->pixclock = vco; vco 751 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c return vco; vco 668 drivers/video/fbdev/cyber2000fb.c int vco; vco 743 drivers/video/fbdev/cyber2000fb.c vco = ref_ps * best_div1 / best_mult; vco 744 drivers/video/fbdev/cyber2000fb.c if ((ref_ps == 40690) && (vco < 5556)) vco 670 drivers/video/fbdev/intelfb/intelfbhw.c u32 m, vco, p; vco 674 drivers/video/fbdev/intelfb/intelfbhw.c vco = pll->ref_clk * m / n; vco 680 drivers/video/fbdev/intelfb/intelfbhw.c return vco / p; vco 106 drivers/video/fbdev/matrox/g450_pll.c unsigned int *vco, unsigned int fout) vco 114 drivers/video/fbdev/matrox/g450_pll.c *vco = vcomax; vco 116 drivers/video/fbdev/matrox/g450_pll.c *vco = fout; vco 131 drivers/video/fbdev/matrox/g450_pll.c *vco = tvco; vco 133 drivers/video/fbdev/matrox/g450_pll.c return g450_nextpll(minfo, pi, vco, 0xFF0000 | p); vco 440 drivers/video/fbdev/matrox/g450_pll.c unsigned int vco; vco 443 drivers/video/fbdev/matrox/g450_pll.c vco = g450_mnp2vco(minfo, mnp); vco 448 drivers/video/fbdev/matrox/g450_pll.c if (vco < pixel_vco) { vco 449 drivers/video/fbdev/matrox/g450_pll.c small = vco; vco 453 drivers/video/fbdev/matrox/g450_pll.c big = vco; vco 463 drivers/video/fbdev/matrox/g450_pll.c delta = pll_freq_delta(fout, g450_vco2f(mnp, vco)); vco 475 drivers/video/fbdev/matrox/g450_pll.c && vco != g450_mnp2vco(minfo, mnparray[idx-1]) vco 476 drivers/video/fbdev/matrox/g450_pll.c && vco < (pi->vcomin * 17 / 16)) {