vclk_div          367 drivers/gpu/drm/meson/meson_vclk.c 	unsigned int vclk_div;
vclk_div          376 drivers/gpu/drm/meson/meson_vclk.c 		.vclk_div = 1,
vclk_div          385 drivers/gpu/drm/meson/meson_vclk.c 		.vclk_div = 1,
vclk_div          394 drivers/gpu/drm/meson/meson_vclk.c 		.vclk_div = 1,
vclk_div          403 drivers/gpu/drm/meson/meson_vclk.c 		.vclk_div = 1,
vclk_div          412 drivers/gpu/drm/meson/meson_vclk.c 		.vclk_div = 1,
vclk_div          421 drivers/gpu/drm/meson/meson_vclk.c 		.vclk_div = 2,
vclk_div          430 drivers/gpu/drm/meson/meson_vclk.c 		.vclk_div = 1,
vclk_div          750 drivers/gpu/drm/meson/meson_vclk.c 			   unsigned int vid_pll_div, unsigned int vclk_div,
vclk_div          828 drivers/gpu/drm/meson/meson_vclk.c 			   VCLK_DIV_MASK, vclk_div - 1);
vclk_div         1045 drivers/gpu/drm/meson/meson_vclk.c 		       params[freq].vclk_div, hdmi_tx_div, venc_div,
vclk_div         1195 drivers/gpu/drm/radeon/evergreen.c 	unsigned fb_div = 0, vclk_div = 0, dclk_div = 0;
vclk_div         1214 drivers/gpu/drm/radeon/evergreen.c 					  &fb_div, &vclk_div, &dclk_div);
vclk_div         1253 drivers/gpu/drm/radeon/evergreen.c 		UPLL_PDIV_A(vclk_div) | UPLL_PDIV_B(dclk_div),
vclk_div          205 drivers/gpu/drm/radeon/r600.c 	unsigned fb_div = 0, ref_div, vclk_div = 0, dclk_div = 0;
vclk_div          234 drivers/gpu/drm/radeon/r600.c 					  &fb_div, &vclk_div, &dclk_div);
vclk_div          261 drivers/gpu/drm/radeon/r600.c 		 UPLL_SW_HILEN(vclk_div >> 1) |
vclk_div          262 drivers/gpu/drm/radeon/r600.c 		 UPLL_SW_LOLEN((vclk_div >> 1) + (vclk_div & 1)) |
vclk_div          979 drivers/gpu/drm/radeon/radeon_uvd.c 		unsigned vclk_div, dclk_div, score;
vclk_div          990 drivers/gpu/drm/radeon/radeon_uvd.c 		vclk_div = radeon_uvd_calc_upll_post_div(vco_freq, vclk,
vclk_div          992 drivers/gpu/drm/radeon/radeon_uvd.c 		if (vclk_div > pd_max)
vclk_div         1002 drivers/gpu/drm/radeon/radeon_uvd.c 		score = vclk - (vco_freq / vclk_div) + dclk - (vco_freq / dclk_div);
vclk_div         1007 drivers/gpu/drm/radeon/radeon_uvd.c 			*optimal_vclk_div = vclk_div;
vclk_div           53 drivers/gpu/drm/radeon/rv770.c 	unsigned fb_div = 0, vclk_div = 0, dclk_div = 0;
vclk_div           73 drivers/gpu/drm/radeon/rv770.c 					  &fb_div, &vclk_div, &dclk_div);
vclk_div           78 drivers/gpu/drm/radeon/rv770.c 	vclk_div -= 1;
vclk_div          101 drivers/gpu/drm/radeon/rv770.c 		 UPLL_SW_HILEN(vclk_div >> 1) |
vclk_div          102 drivers/gpu/drm/radeon/rv770.c 		 UPLL_SW_LOLEN((vclk_div >> 1) + (vclk_div & 1)) |
vclk_div         6999 drivers/gpu/drm/radeon/si.c 	unsigned fb_div = 0, vclk_div = 0, dclk_div = 0;
vclk_div         7017 drivers/gpu/drm/radeon/si.c 					  &fb_div, &vclk_div, &dclk_div);
vclk_div         7058 drivers/gpu/drm/radeon/si.c 		UPLL_PDIV_A(vclk_div) | UPLL_PDIV_B(dclk_div),