vclk 560 drivers/gpu/drm/amd/amdgpu/amdgpu.h int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); vclk 568 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].vclk = vclk 60 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h u32 vclk; vclk 162 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h u32 vclk; vclk 1335 drivers/gpu/drm/amd/amdgpu/cik.c static int cik_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) vclk 1339 drivers/gpu/drm/amd/amdgpu/cik.c r = cik_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS); vclk 919 drivers/gpu/drm/amd/amdgpu/kv_dpm.c pi->uvd_level[i].VclkFrequency = cpu_to_be32(table->entries[i].vclk); vclk 924 drivers/gpu/drm/amd/amdgpu/kv_dpm.c (u8)kv_get_clk_bypass(adev, table->entries[i].vclk); vclk 929 drivers/gpu/drm/amd/amdgpu/kv_dpm.c table->entries[i].vclk, false, ÷rs); vclk 2288 drivers/gpu/drm/amd/amdgpu/kv_dpm.c pi->video_start = new_rps->dclk || new_rps->vclk || vclk 2664 drivers/gpu/drm/amd/amdgpu/kv_dpm.c rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); vclk 2667 drivers/gpu/drm/amd/amdgpu/kv_dpm.c rps->vclk = 0; vclk 2901 drivers/gpu/drm/amd/amdgpu/kv_dpm.c printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); vclk 3274 drivers/gpu/drm/amd/amdgpu/kv_dpm.c *equal = ((cps->vclk == rps->vclk) && (cps->dclk == rps->dclk)); vclk 332 drivers/gpu/drm/amd/amdgpu/nv.c static int nv_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) vclk 1231 drivers/gpu/drm/amd/amdgpu/si.c static int si_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) vclk 2372 drivers/gpu/drm/amd/amdgpu/si_dpm.c amdgpu_state->vclk && amdgpu_state->dclk) vclk 3179 drivers/gpu/drm/amd/amdgpu/si_dpm.c if ((new_ps->vclk == old_ps->vclk) && vclk 3187 drivers/gpu/drm/amd/amdgpu/si_dpm.c amdgpu_asic_set_uvd_clocks(adev, new_ps->vclk, new_ps->dclk); vclk 3197 drivers/gpu/drm/amd/amdgpu/si_dpm.c if ((new_ps->vclk == old_ps->vclk) && vclk 3205 drivers/gpu/drm/amd/amdgpu/si_dpm.c amdgpu_asic_set_uvd_clocks(adev, new_ps->vclk, new_ps->dclk); vclk 3480 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (rps->vclk || rps->dclk) { vclk 5631 drivers/gpu/drm/amd/amdgpu/si_dpm.c if ((amdgpu_state->vclk != 0) || (amdgpu_state->dclk != 0)) vclk 5668 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (amdgpu_state->vclk && amdgpu_state->dclk) { vclk 7116 drivers/gpu/drm/amd/amdgpu/si_dpm.c rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); vclk 7119 drivers/gpu/drm/amd/amdgpu/si_dpm.c rps->vclk = RV770_DEFAULT_VCLK_FREQ; vclk 7122 drivers/gpu/drm/amd/amdgpu/si_dpm.c rps->vclk = 0; vclk 7498 drivers/gpu/drm/amd/amdgpu/si_dpm.c seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); vclk 7905 drivers/gpu/drm/amd/amdgpu/si_dpm.c DRM_INFO("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); vclk 7977 drivers/gpu/drm/amd/amdgpu/si_dpm.c *equal = ((cps->vclk == rps->vclk) && (cps->dclk == rps->dclk)); vclk 605 drivers/gpu/drm/amd/amdgpu/soc15.c static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) vclk 771 drivers/gpu/drm/amd/amdgpu/vi.c static int vi_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) vclk 776 drivers/gpu/drm/amd/amdgpu/vi.c r = vi_set_uvd_clock(adev, vclk, ixGNB_CLK2_DFS_CNTL, ixGNB_CLK2_STATUS); vclk 784 drivers/gpu/drm/amd/amdgpu/vi.c r = vi_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS); vclk 60 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr_ppt.h uint32_t vclk; /* UVD V-clock */ vclk 722 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c mm_table_record->vclk = le32_to_cpu(mm_dependency_record->ulVClk); vclk 1129 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c uvd_table->entries[i].vclk = ((unsigned long)entry->ucVClkHigh << 16) vclk 791 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c smu10_ps->uvd_clocks.vclk = ps->uvd_clocks.VCLK; vclk 97 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h uint32_t vclk; vclk 3256 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c ps->uvd_clks.vclk = state->uvd_clocks.VCLK; vclk 3404 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c ps->uvd_clks.vclk = state->uvd_clocks.VCLK; vclk 4223 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c *equal = ((psa->uvd_clks.vclk == psb->uvd_clks.vclk) && (psa->uvd_clks.dclk == psb->uvd_clks.dclk)); vclk 68 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h uint32_t vclk; vclk 140 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c if (clock <= ptable->entries[i].vclk) vclk 148 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c if (clock >= ptable->entries[i].vclk) vclk 511 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c (i < uvd_table->count) ? uvd_table->entries[i].vclk : 0; vclk 595 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c clock = table->entries[level].vclk; vclk 597 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c clock = table->entries[table->count - 1].vclk; vclk 1386 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c smu8_ps->uvd_clocks.vclk = ps->uvd_clocks.VCLK; vclk 1690 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c uint32_t sclk, vclk, dclk, ecclk, tmp, activity_percent; vclk 1724 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c vclk = uvd_table->entries[uvd_index].vclk; vclk 1725 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c *((uint32_t *)value) = vclk; vclk 1851 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c ptable->entries[ptable->count - 1].vclk; vclk 114 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h uint32_t vclk; vclk 1385 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c dep_mm_table->entries[i].vclk) { vclk 1387 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c dep_mm_table->entries[i].vclk; vclk 2063 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c if (dep_table->entries[i].vclk == vclk 3118 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c ps->uvd_clks.vclk = state->uvd_clocks.VCLK; vclk 4671 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c *equal = ((psa->uvd_clks.vclk == psb->uvd_clks.vclk) && (psa->uvd_clks.dclk == psb->uvd_clks.dclk)); vclk 96 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h uint32_t vclk; vclk 370 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c mm_table->entries[i].vclk = le32_to_cpu(mm_dependency_record->ulVClk); vclk 113 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h uint32_t vclk; vclk 131 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h uint32_t vclk; vclk 217 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h uint32_t vclk; vclk 109 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t vclk; vclk 136 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t vclk; vclk 183 drivers/gpu/drm/amd/powerplay/inc/power_state.h unsigned long vclk; vclk 639 drivers/gpu/drm/amd/powerplay/smu_v11_0.c smu->smu_table.boot_values.vclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000; vclk 1529 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uvd_table->entries[count].vclk; vclk 1574 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk; vclk 1410 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk; vclk 1324 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk; vclk 1334 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk; vclk 795 drivers/gpu/drm/amd/powerplay/vega20_ppt.c single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100; vclk 50 drivers/gpu/drm/exynos/exynos7_drm_decon.c struct clk *vclk; vclk 147 drivers/gpu/drm/exynos/exynos7_drm_decon.c clkdiv = DIV_ROUND_UP(clk_get_rate(ctx->vclk), ideal_clk); vclk 718 drivers/gpu/drm/exynos/exynos7_drm_decon.c ctx->vclk = devm_clk_get(dev, "decon0_vclk"); vclk 719 drivers/gpu/drm/exynos/exynos7_drm_decon.c if (IS_ERR(ctx->vclk)) { vclk 721 drivers/gpu/drm/exynos/exynos7_drm_decon.c ret = PTR_ERR(ctx->vclk); vclk 786 drivers/gpu/drm/exynos/exynos7_drm_decon.c clk_disable_unprepare(ctx->vclk); vclk 820 drivers/gpu/drm/exynos/exynos7_drm_decon.c ret = clk_prepare_enable(ctx->vclk); vclk 253 drivers/gpu/drm/nouveau/dispnv04/arb.c nouveau_calc_arb(struct drm_device *dev, int vclk, int bpp, int *burst, int *lwm) vclk 258 drivers/gpu/drm/nouveau/dispnv04/arb.c nv04_update_arb(dev, vclk, bpp, burst, lwm); vclk 56 drivers/gpu/drm/nouveau/dispnv04/hw.h extern void nouveau_calc_arb(struct drm_device *, int vclk, int bpp, vclk 2756 drivers/gpu/drm/radeon/btc_dpm.c seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); vclk 2660 drivers/gpu/drm/radeon/ci_dpm.c rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].vclk; vclk 5461 drivers/gpu/drm/radeon/ci_dpm.c rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); vclk 5464 drivers/gpu/drm/radeon/ci_dpm.c rps->vclk = 0; vclk 5965 drivers/gpu/drm/radeon/ci_dpm.c printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); vclk 9456 drivers/gpu/drm/radeon/cik.c int cik_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk) vclk 9460 drivers/gpu/drm/radeon/cik.c r = cik_set_uvd_clock(rdev, vclk, CG_VCLK_CNTL, CG_VCLK_STATUS); vclk 1169 drivers/gpu/drm/radeon/evergreen.c int sumo_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk) vclk 1174 drivers/gpu/drm/radeon/evergreen.c r = sumo_set_uvd_clock(rdev, vclk, CG_VCLK_CNTL, CG_VCLK_STATUS); vclk 1178 drivers/gpu/drm/radeon/evergreen.c cg_scratch |= vclk / 100; /* Mhz */ vclk 1192 drivers/gpu/drm/radeon/evergreen.c int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk) vclk 1206 drivers/gpu/drm/radeon/evergreen.c if (!vclk || !dclk) { vclk 1212 drivers/gpu/drm/radeon/evergreen.c r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 125000, 250000, vclk 837 drivers/gpu/drm/radeon/kv_dpm.c pi->uvd_level[i].VclkFrequency = cpu_to_be32(table->entries[i].vclk); vclk 842 drivers/gpu/drm/radeon/kv_dpm.c (u8)kv_get_clk_bypass(rdev, table->entries[i].vclk); vclk 847 drivers/gpu/drm/radeon/kv_dpm.c table->entries[i].vclk, false, ÷rs); vclk 2223 drivers/gpu/drm/radeon/kv_dpm.c pi->video_start = new_rps->dclk || new_rps->vclk || vclk 2596 drivers/gpu/drm/radeon/kv_dpm.c rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); vclk 2599 drivers/gpu/drm/radeon/kv_dpm.c rps->vclk = 0; vclk 2857 drivers/gpu/drm/radeon/kv_dpm.c printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); vclk 3515 drivers/gpu/drm/radeon/ni_dpm.c if ((new_ps->vclk == old_ps->vclk) && vclk 3523 drivers/gpu/drm/radeon/ni_dpm.c radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); vclk 3533 drivers/gpu/drm/radeon/ni_dpm.c if ((new_ps->vclk == old_ps->vclk) && vclk 3541 drivers/gpu/drm/radeon/ni_dpm.c radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); vclk 3904 drivers/gpu/drm/radeon/ni_dpm.c rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); vclk 3907 drivers/gpu/drm/radeon/ni_dpm.c rps->vclk = RV770_DEFAULT_VCLK_FREQ; vclk 3910 drivers/gpu/drm/radeon/ni_dpm.c rps->vclk = 0; vclk 4291 drivers/gpu/drm/radeon/ni_dpm.c printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); vclk 4319 drivers/gpu/drm/radeon/ni_dpm.c seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); vclk 203 drivers/gpu/drm/radeon/r600.c int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk) vclk 221 drivers/gpu/drm/radeon/r600.c if (!vclk || !dclk) { vclk 232 drivers/gpu/drm/radeon/r600.c r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 50000, 160000, vclk 1160 drivers/gpu/drm/radeon/r600_dpm.c rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].vclk = vclk 1338 drivers/gpu/drm/radeon/radeon.h u32 vclk; vclk 1424 drivers/gpu/drm/radeon/radeon.h u32 vclk; vclk 1695 drivers/gpu/drm/radeon/radeon.h unsigned vclk, unsigned dclk, vclk 1960 drivers/gpu/drm/radeon/radeon.h int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk); vclk 411 drivers/gpu/drm/radeon/radeon_asic.h int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); vclk 478 drivers/gpu/drm/radeon/radeon_asic.h int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); vclk 535 drivers/gpu/drm/radeon/radeon_asic.h int sumo_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); vclk 536 drivers/gpu/drm/radeon/radeon_asic.h int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); vclk 749 drivers/gpu/drm/radeon/radeon_asic.h int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); vclk 787 drivers/gpu/drm/radeon/radeon_asic.h int cik_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); vclk 960 drivers/gpu/drm/radeon/radeon_uvd.c unsigned vclk, unsigned dclk, vclk 975 drivers/gpu/drm/radeon/radeon_uvd.c vco_min = max(max(vco_min, vclk), dclk); vclk 990 drivers/gpu/drm/radeon/radeon_uvd.c vclk_div = radeon_uvd_calc_upll_post_div(vco_freq, vclk, vclk 1002 drivers/gpu/drm/radeon/radeon_uvd.c score = vclk - (vco_freq / vclk_div) + dclk - (vco_freq / dclk_div); vclk 572 drivers/gpu/drm/radeon/rs780_dpm.c if ((new_ps->vclk == old_ps->vclk) && vclk 579 drivers/gpu/drm/radeon/rs780_dpm.c radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); vclk 589 drivers/gpu/drm/radeon/rs780_dpm.c if ((new_ps->vclk == old_ps->vclk) && vclk 596 drivers/gpu/drm/radeon/rs780_dpm.c radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); vclk 729 drivers/gpu/drm/radeon/rs780_dpm.c rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); vclk 732 drivers/gpu/drm/radeon/rs780_dpm.c rps->vclk = 0; vclk 737 drivers/gpu/drm/radeon/rs780_dpm.c if ((rps->vclk == 0) || (rps->dclk == 0)) { vclk 738 drivers/gpu/drm/radeon/rs780_dpm.c rps->vclk = RS780_DEFAULT_VCLK_FREQ; vclk 947 drivers/gpu/drm/radeon/rs780_dpm.c printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); vclk 996 drivers/gpu/drm/radeon/rs780_dpm.c seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); vclk 1518 drivers/gpu/drm/radeon/rv6xx_dpm.c if ((new_ps->vclk == old_ps->vclk) && vclk 1525 drivers/gpu/drm/radeon/rv6xx_dpm.c radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); vclk 1535 drivers/gpu/drm/radeon/rv6xx_dpm.c if ((new_ps->vclk == old_ps->vclk) && vclk 1542 drivers/gpu/drm/radeon/rv6xx_dpm.c radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); vclk 1803 drivers/gpu/drm/radeon/rv6xx_dpm.c rps->vclk = RV6XX_DEFAULT_VCLK_FREQ; vclk 1806 drivers/gpu/drm/radeon/rv6xx_dpm.c rps->vclk = 0; vclk 2015 drivers/gpu/drm/radeon/rv6xx_dpm.c printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); vclk 2047 drivers/gpu/drm/radeon/rv6xx_dpm.c seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); vclk 49 drivers/gpu/drm/radeon/rv770.c int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); vclk 51 drivers/gpu/drm/radeon/rv770.c int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk) vclk 58 drivers/gpu/drm/radeon/rv770.c return evergreen_set_uvd_clocks(rdev, vclk, dclk); vclk 65 drivers/gpu/drm/radeon/rv770.c if (!vclk || !dclk) { vclk 71 drivers/gpu/drm/radeon/rv770.c r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 50000, 160000, vclk 1438 drivers/gpu/drm/radeon/rv770_dpm.c if ((new_ps->vclk == old_ps->vclk) && vclk 1445 drivers/gpu/drm/radeon/rv770_dpm.c radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); vclk 1455 drivers/gpu/drm/radeon/rv770_dpm.c if ((new_ps->vclk == old_ps->vclk) && vclk 1462 drivers/gpu/drm/radeon/rv770_dpm.c radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); vclk 2153 drivers/gpu/drm/radeon/rv770_dpm.c rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); vclk 2156 drivers/gpu/drm/radeon/rv770_dpm.c rps->vclk = 0; vclk 2161 drivers/gpu/drm/radeon/rv770_dpm.c if ((rps->vclk == 0) || (rps->dclk == 0)) { vclk 2162 drivers/gpu/drm/radeon/rv770_dpm.c rps->vclk = RV770_DEFAULT_VCLK_FREQ; vclk 2440 drivers/gpu/drm/radeon/rv770_dpm.c printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); vclk 2484 drivers/gpu/drm/radeon/rv770_dpm.c seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); vclk 6997 drivers/gpu/drm/radeon/si.c int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk) vclk 7010 drivers/gpu/drm/radeon/si.c if (!vclk || !dclk) { vclk 7015 drivers/gpu/drm/radeon/si.c r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 125000, 250000, vclk 2282 drivers/gpu/drm/radeon/si_dpm.c radeon_state->vclk && radeon_state->dclk) vclk 3021 drivers/gpu/drm/radeon/si_dpm.c if (rps->vclk || rps->dclk) { vclk 5169 drivers/gpu/drm/radeon/si_dpm.c if ((radeon_state->vclk != 0) || (radeon_state->dclk != 0)) vclk 5206 drivers/gpu/drm/radeon/si_dpm.c if (radeon_state->vclk && radeon_state->dclk) { vclk 6716 drivers/gpu/drm/radeon/si_dpm.c rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); vclk 6719 drivers/gpu/drm/radeon/si_dpm.c rps->vclk = RV770_DEFAULT_VCLK_FREQ; vclk 6722 drivers/gpu/drm/radeon/si_dpm.c rps->vclk = 0; vclk 7107 drivers/gpu/drm/radeon/si_dpm.c seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); vclk 824 drivers/gpu/drm/radeon/sumo_dpm.c radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk); vclk 840 drivers/gpu/drm/radeon/sumo_dpm.c if ((new_rps->vclk == old_rps->vclk) && vclk 858 drivers/gpu/drm/radeon/sumo_dpm.c if ((new_rps->vclk == old_rps->vclk) && vclk 1414 drivers/gpu/drm/radeon/sumo_dpm.c rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); vclk 1417 drivers/gpu/drm/radeon/sumo_dpm.c rps->vclk = 0; vclk 1802 drivers/gpu/drm/radeon/sumo_dpm.c printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); vclk 1825 drivers/gpu/drm/radeon/sumo_dpm.c seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); vclk 1833 drivers/gpu/drm/radeon/sumo_dpm.c seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); vclk 899 drivers/gpu/drm/radeon/trinity_dpm.c if ((rps->vclk == 0) && (rps->dclk == 0)) vclk 911 drivers/gpu/drm/radeon/trinity_dpm.c if ((rps1->vclk == rps2->vclk) && vclk 944 drivers/gpu/drm/radeon/trinity_dpm.c radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk); vclk 955 drivers/gpu/drm/radeon/trinity_dpm.c radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk); vclk 1459 drivers/gpu/drm/radeon/trinity_dpm.c if ((rps->vclk == pi->sys_info.uvd_clock_table_entries[i].vclk) && vclk 1693 drivers/gpu/drm/radeon/trinity_dpm.c rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); vclk 1696 drivers/gpu/drm/radeon/trinity_dpm.c rps->vclk = 0; vclk 1934 drivers/gpu/drm/radeon/trinity_dpm.c pi->sys_info.uvd_clock_table_entries[i].vclk = vclk 2020 drivers/gpu/drm/radeon/trinity_dpm.c printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); vclk 2045 drivers/gpu/drm/radeon/trinity_dpm.c seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); vclk 69 drivers/gpu/drm/radeon/trinity_dpm.h u32 vclk; vclk 210 drivers/media/platform/aspeed-video.c struct clk *vclk; vclk 494 drivers/media/platform/aspeed-video.c clk_disable(video->vclk); vclk 507 drivers/media/platform/aspeed-video.c clk_enable(video->vclk); vclk 1618 drivers/media/platform/aspeed-video.c video->vclk = devm_clk_get(dev, "vclk"); vclk 1619 drivers/media/platform/aspeed-video.c if (IS_ERR(video->vclk)) { vclk 1621 drivers/media/platform/aspeed-video.c rc = PTR_ERR(video->vclk); vclk 1625 drivers/media/platform/aspeed-video.c rc = clk_prepare(video->vclk); vclk 1650 drivers/media/platform/aspeed-video.c clk_unprepare(video->vclk); vclk 1701 drivers/media/platform/aspeed-video.c clk_unprepare(video->vclk); vclk 433 drivers/video/fbdev/aty/aty128fb.c u32 vclk; vclk 1372 drivers/video/fbdev/aty/aty128fb.c u32 vclk; /* in .01 MHz */ vclk 1376 drivers/video/fbdev/aty/aty128fb.c vclk = 100000000 / period_in_ps; /* convert units to 10 kHz */ vclk 1379 drivers/video/fbdev/aty/aty128fb.c if (vclk > c.ppll_max) vclk 1380 drivers/video/fbdev/aty/aty128fb.c vclk = c.ppll_max; vclk 1381 drivers/video/fbdev/aty/aty128fb.c if (vclk * 12 < c.ppll_min) vclk 1382 drivers/video/fbdev/aty/aty128fb.c vclk = c.ppll_min/12; vclk 1386 drivers/video/fbdev/aty/aty128fb.c output_freq = post_dividers[i] * vclk; vclk 1401 drivers/video/fbdev/aty/aty128fb.c pll->vclk = vclk; vclk 1405 drivers/video/fbdev/aty/aty128fb.c pll->feedback_divider, vclk, output_freq, vclk 1415 drivers/video/fbdev/aty/aty128fb.c var->pixclock = 100000000 / pll->vclk; vclk 1445 drivers/video/fbdev/aty/aty128fb.c d = pll->vclk * bpp; vclk 584 drivers/video/fbdev/aty/radeon_base.c unsigned long long hz, vclk; vclk 624 drivers/video/fbdev/aty/radeon_base.c vclk = (long long)hTotal * (long long)vTotal * hz; vclk 676 drivers/video/fbdev/aty/radeon_base.c vclk *= denom; vclk 677 drivers/video/fbdev/aty/radeon_base.c do_div(vclk, 1000 * num); vclk 678 drivers/video/fbdev/aty/radeon_base.c xtal = vclk; vclk 1141 drivers/video/fbdev/tridentfb.c unsigned long vclk; vclk 1301 drivers/video/fbdev/tridentfb.c vclk = PICOS2KHZ(info->var.pixclock); vclk 1307 drivers/video/fbdev/tridentfb.c vclk *= 2; vclk 1309 drivers/video/fbdev/tridentfb.c set_vclk(par, vclk); vclk 141 drivers/video/fbdev/via/chip.h u32 vclk; /*panel mode clock value */ vclk 552 drivers/video/fbdev/via/lcd.c plvds_setting_info->vclk = clock; vclk 186 drivers/video/fbdev/via/vt1636.c index = get_clk_range_index(plvds_setting_info->vclk); vclk 210 drivers/video/fbdev/via/vt1636.c index = get_clk_range_index(plvds_setting_info->vclk); vclk 227 drivers/video/fbdev/via/vt1636.c index = get_clk_range_index(plvds_setting_info->vclk);