vce_dpm_enable_mask  164 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h 	uint32_t  vce_dpm_enable_mask;
vce_dpm_enable_mask  174 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h 	uint32_t  vce_dpm_enable_mask;
vce_dpm_enable_mask  153 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h 	uint32_t  vce_dpm_enable_mask;
vce_dpm_enable_mask  206 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h 	uint32_t  vce_dpm_enable_mask;
vce_dpm_enable_mask 2907 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	data->dpm_level_enable_mask.vce_dpm_enable_mask = 0;
vce_dpm_enable_mask 2911 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 			data->dpm_level_enable_mask.vce_dpm_enable_mask |= 1 << i;
vce_dpm_enable_mask 2916 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 				data->dpm_level_enable_mask.vce_dpm_enable_mask);
vce_dpm_enable_mask 3992 drivers/gpu/drm/radeon/ci_dpm.c 		pi->dpm_level_enable_mask.vce_dpm_enable_mask = 0;
vce_dpm_enable_mask 3995 drivers/gpu/drm/radeon/ci_dpm.c 				pi->dpm_level_enable_mask.vce_dpm_enable_mask |= 1 << i;
vce_dpm_enable_mask 4004 drivers/gpu/drm/radeon/ci_dpm.c 						  pi->dpm_level_enable_mask.vce_dpm_enable_mask);
vce_dpm_enable_mask  108 drivers/gpu/drm/radeon/ci_dpm.h 	u32 vce_dpm_enable_mask;