vc4_state         387 drivers/gpu/drm/vc4/vc4_crtc.c 	struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
vc4_state         413 drivers/gpu/drm/vc4/vc4_crtc.c 		if (vc4_state->feed_txp)
vc4_state         423 drivers/gpu/drm/vc4/vc4_crtc.c 	if (!vc4_state->feed_txp)
vc4_state         509 drivers/gpu/drm/vc4/vc4_crtc.c 	struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
vc4_state         511 drivers/gpu/drm/vc4/vc4_crtc.c 	vc4_state->txp_armed = true;
vc4_state         519 drivers/gpu/drm/vc4/vc4_crtc.c 	struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
vc4_state         530 drivers/gpu/drm/vc4/vc4_crtc.c 		if (!vc4_state->feed_txp || vc4_state->txp_armed) {
vc4_state         536 drivers/gpu/drm/vc4/vc4_crtc.c 			  vc4_state->mm.start);
vc4_state         541 drivers/gpu/drm/vc4/vc4_crtc.c 			  vc4_state->mm.start);
vc4_state         551 drivers/gpu/drm/vc4/vc4_crtc.c 	struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
vc4_state         571 drivers/gpu/drm/vc4/vc4_crtc.c 		  (vc4_state->feed_txp ? SCALER_DISPCTRLX_ONESHOT : 0));
vc4_state         576 drivers/gpu/drm/vc4/vc4_crtc.c 	if (!vc4_state->feed_txp)
vc4_state         598 drivers/gpu/drm/vc4/vc4_crtc.c 	struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
vc4_state         603 drivers/gpu/drm/vc4/vc4_crtc.c 	*left = vc4_state->margins.left;
vc4_state         604 drivers/gpu/drm/vc4/vc4_crtc.c 	*right = vc4_state->margins.right;
vc4_state         605 drivers/gpu/drm/vc4/vc4_crtc.c 	*top = vc4_state->margins.top;
vc4_state         606 drivers/gpu/drm/vc4/vc4_crtc.c 	*bottom = vc4_state->margins.bottom;
vc4_state         628 drivers/gpu/drm/vc4/vc4_crtc.c 	struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
vc4_state         651 drivers/gpu/drm/vc4/vc4_crtc.c 	ret = drm_mm_insert_node(&vc4->hvs->dlist_mm, &vc4_state->mm,
vc4_state         666 drivers/gpu/drm/vc4/vc4_crtc.c 			vc4_state->feed_txp = true;
vc4_state         669 drivers/gpu/drm/vc4/vc4_crtc.c 			vc4_state->feed_txp = false;
vc4_state         672 drivers/gpu/drm/vc4/vc4_crtc.c 		vc4_state->margins.left = conn_state->tv.margins.left;
vc4_state         673 drivers/gpu/drm/vc4/vc4_crtc.c 		vc4_state->margins.right = conn_state->tv.margins.right;
vc4_state         674 drivers/gpu/drm/vc4/vc4_crtc.c 		vc4_state->margins.top = conn_state->tv.margins.top;
vc4_state         675 drivers/gpu/drm/vc4/vc4_crtc.c 		vc4_state->margins.bottom = conn_state->tv.margins.bottom;
vc4_state         688 drivers/gpu/drm/vc4/vc4_crtc.c 	struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
vc4_state         693 drivers/gpu/drm/vc4/vc4_crtc.c 	u32 __iomem *dlist_start = vc4->hvs->dlist + vc4_state->mm.start;
vc4_state         723 drivers/gpu/drm/vc4/vc4_crtc.c 	WARN_ON_ONCE(dlist_next - dlist_start != vc4_state->mm.size);
vc4_state         786 drivers/gpu/drm/vc4/vc4_crtc.c 	struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
vc4_state         792 drivers/gpu/drm/vc4/vc4_crtc.c 	    (vc4_state->mm.start == HVS_READ(SCALER_DISPLACTX(chan)) ||
vc4_state         793 drivers/gpu/drm/vc4/vc4_crtc.c 	     vc4_state->feed_txp)) {
vc4_state         977 drivers/gpu/drm/vc4/vc4_crtc.c 	struct vc4_crtc_state *vc4_state, *old_vc4_state;
vc4_state         979 drivers/gpu/drm/vc4/vc4_crtc.c 	vc4_state = kzalloc(sizeof(*vc4_state), GFP_KERNEL);
vc4_state         980 drivers/gpu/drm/vc4/vc4_crtc.c 	if (!vc4_state)
vc4_state         984 drivers/gpu/drm/vc4/vc4_crtc.c 	vc4_state->feed_txp = old_vc4_state->feed_txp;
vc4_state         985 drivers/gpu/drm/vc4/vc4_crtc.c 	vc4_state->margins = old_vc4_state->margins;
vc4_state         987 drivers/gpu/drm/vc4/vc4_crtc.c 	__drm_atomic_helper_crtc_duplicate_state(crtc, &vc4_state->base);
vc4_state         988 drivers/gpu/drm/vc4/vc4_crtc.c 	return &vc4_state->base;
vc4_state         995 drivers/gpu/drm/vc4/vc4_crtc.c 	struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
vc4_state         997 drivers/gpu/drm/vc4/vc4_crtc.c 	if (vc4_state->mm.allocated) {
vc4_state        1001 drivers/gpu/drm/vc4/vc4_crtc.c 		drm_mm_remove_node(&vc4_state->mm);
vc4_state         147 drivers/gpu/drm/vc4/vc4_plane.c 	struct vc4_plane_state *vc4_state;
vc4_state         152 drivers/gpu/drm/vc4/vc4_plane.c 	vc4_state = kmemdup(plane->state, sizeof(*vc4_state), GFP_KERNEL);
vc4_state         153 drivers/gpu/drm/vc4/vc4_plane.c 	if (!vc4_state)
vc4_state         156 drivers/gpu/drm/vc4/vc4_plane.c 	memset(&vc4_state->lbm, 0, sizeof(vc4_state->lbm));
vc4_state         157 drivers/gpu/drm/vc4/vc4_plane.c 	vc4_state->dlist_initialized = 0;
vc4_state         159 drivers/gpu/drm/vc4/vc4_plane.c 	__drm_atomic_helper_plane_duplicate_state(plane, &vc4_state->base);
vc4_state         161 drivers/gpu/drm/vc4/vc4_plane.c 	if (vc4_state->dlist) {
vc4_state         162 drivers/gpu/drm/vc4/vc4_plane.c 		vc4_state->dlist = kmemdup(vc4_state->dlist,
vc4_state         163 drivers/gpu/drm/vc4/vc4_plane.c 					   vc4_state->dlist_count * 4,
vc4_state         165 drivers/gpu/drm/vc4/vc4_plane.c 		if (!vc4_state->dlist) {
vc4_state         166 drivers/gpu/drm/vc4/vc4_plane.c 			kfree(vc4_state);
vc4_state         169 drivers/gpu/drm/vc4/vc4_plane.c 		vc4_state->dlist_size = vc4_state->dlist_count;
vc4_state         172 drivers/gpu/drm/vc4/vc4_plane.c 	return &vc4_state->base;
vc4_state         179 drivers/gpu/drm/vc4/vc4_plane.c 	struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
vc4_state         181 drivers/gpu/drm/vc4/vc4_plane.c 	if (vc4_state->lbm.allocated) {
vc4_state         185 drivers/gpu/drm/vc4/vc4_plane.c 		drm_mm_remove_node(&vc4_state->lbm);
vc4_state         189 drivers/gpu/drm/vc4/vc4_plane.c 	kfree(vc4_state->dlist);
vc4_state         190 drivers/gpu/drm/vc4/vc4_plane.c 	__drm_atomic_helper_plane_destroy_state(&vc4_state->base);
vc4_state         197 drivers/gpu/drm/vc4/vc4_plane.c 	struct vc4_plane_state *vc4_state;
vc4_state         201 drivers/gpu/drm/vc4/vc4_plane.c 	vc4_state = kzalloc(sizeof(*vc4_state), GFP_KERNEL);
vc4_state         202 drivers/gpu/drm/vc4/vc4_plane.c 	if (!vc4_state)
vc4_state         205 drivers/gpu/drm/vc4/vc4_plane.c 	__drm_atomic_helper_plane_reset(plane, &vc4_state->base);
vc4_state         208 drivers/gpu/drm/vc4/vc4_plane.c static void vc4_dlist_write(struct vc4_plane_state *vc4_state, u32 val)
vc4_state         210 drivers/gpu/drm/vc4/vc4_plane.c 	if (vc4_state->dlist_count == vc4_state->dlist_size) {
vc4_state         211 drivers/gpu/drm/vc4/vc4_plane.c 		u32 new_size = max(4u, vc4_state->dlist_count * 2);
vc4_state         216 drivers/gpu/drm/vc4/vc4_plane.c 		memcpy(new_dlist, vc4_state->dlist, vc4_state->dlist_count * 4);
vc4_state         218 drivers/gpu/drm/vc4/vc4_plane.c 		kfree(vc4_state->dlist);
vc4_state         219 drivers/gpu/drm/vc4/vc4_plane.c 		vc4_state->dlist = new_dlist;
vc4_state         220 drivers/gpu/drm/vc4/vc4_plane.c 		vc4_state->dlist_size = new_size;
vc4_state         223 drivers/gpu/drm/vc4/vc4_plane.c 	vc4_state->dlist[vc4_state->dlist_count++] = val;
vc4_state         233 drivers/gpu/drm/vc4/vc4_plane.c 	struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
vc4_state         235 drivers/gpu/drm/vc4/vc4_plane.c 	switch (vc4_state->x_scaling[plane] << 2 | vc4_state->y_scaling[plane]) {
vc4_state         309 drivers/gpu/drm/vc4/vc4_plane.c 	struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
vc4_state         332 drivers/gpu/drm/vc4/vc4_plane.c 		vc4_state->offsets[i] = bo->paddr + fb->offsets[i];
vc4_state         342 drivers/gpu/drm/vc4/vc4_plane.c 	vc4_state->src_x = state->src.x1 >> 16;
vc4_state         343 drivers/gpu/drm/vc4/vc4_plane.c 	vc4_state->src_y = state->src.y1 >> 16;
vc4_state         344 drivers/gpu/drm/vc4/vc4_plane.c 	vc4_state->src_w[0] = (state->src.x2 - state->src.x1) >> 16;
vc4_state         345 drivers/gpu/drm/vc4/vc4_plane.c 	vc4_state->src_h[0] = (state->src.y2 - state->src.y1) >> 16;
vc4_state         347 drivers/gpu/drm/vc4/vc4_plane.c 	vc4_state->crtc_x = state->dst.x1;
vc4_state         348 drivers/gpu/drm/vc4/vc4_plane.c 	vc4_state->crtc_y = state->dst.y1;
vc4_state         349 drivers/gpu/drm/vc4/vc4_plane.c 	vc4_state->crtc_w = state->dst.x2 - state->dst.x1;
vc4_state         350 drivers/gpu/drm/vc4/vc4_plane.c 	vc4_state->crtc_h = state->dst.y2 - state->dst.y1;
vc4_state         356 drivers/gpu/drm/vc4/vc4_plane.c 	vc4_state->x_scaling[0] = vc4_get_scaling_mode(vc4_state->src_w[0],
vc4_state         357 drivers/gpu/drm/vc4/vc4_plane.c 						       vc4_state->crtc_w);
vc4_state         358 drivers/gpu/drm/vc4/vc4_plane.c 	vc4_state->y_scaling[0] = vc4_get_scaling_mode(vc4_state->src_h[0],
vc4_state         359 drivers/gpu/drm/vc4/vc4_plane.c 						       vc4_state->crtc_h);
vc4_state         361 drivers/gpu/drm/vc4/vc4_plane.c 	vc4_state->is_unity = (vc4_state->x_scaling[0] == VC4_SCALING_NONE &&
vc4_state         362 drivers/gpu/drm/vc4/vc4_plane.c 			       vc4_state->y_scaling[0] == VC4_SCALING_NONE);
vc4_state         365 drivers/gpu/drm/vc4/vc4_plane.c 		vc4_state->is_yuv = true;
vc4_state         367 drivers/gpu/drm/vc4/vc4_plane.c 		vc4_state->src_w[1] = vc4_state->src_w[0] / h_subsample;
vc4_state         368 drivers/gpu/drm/vc4/vc4_plane.c 		vc4_state->src_h[1] = vc4_state->src_h[0] / v_subsample;
vc4_state         370 drivers/gpu/drm/vc4/vc4_plane.c 		vc4_state->x_scaling[1] =
vc4_state         371 drivers/gpu/drm/vc4/vc4_plane.c 			vc4_get_scaling_mode(vc4_state->src_w[1],
vc4_state         372 drivers/gpu/drm/vc4/vc4_plane.c 					     vc4_state->crtc_w);
vc4_state         373 drivers/gpu/drm/vc4/vc4_plane.c 		vc4_state->y_scaling[1] =
vc4_state         374 drivers/gpu/drm/vc4/vc4_plane.c 			vc4_get_scaling_mode(vc4_state->src_h[1],
vc4_state         375 drivers/gpu/drm/vc4/vc4_plane.c 					     vc4_state->crtc_h);
vc4_state         383 drivers/gpu/drm/vc4/vc4_plane.c 		if (vc4_state->x_scaling[1] == VC4_SCALING_NONE)
vc4_state         384 drivers/gpu/drm/vc4/vc4_plane.c 			vc4_state->x_scaling[1] = VC4_SCALING_PPF;
vc4_state         386 drivers/gpu/drm/vc4/vc4_plane.c 		vc4_state->is_yuv = false;
vc4_state         387 drivers/gpu/drm/vc4/vc4_plane.c 		vc4_state->x_scaling[1] = VC4_SCALING_NONE;
vc4_state         388 drivers/gpu/drm/vc4/vc4_plane.c 		vc4_state->y_scaling[1] = VC4_SCALING_NONE;
vc4_state         394 drivers/gpu/drm/vc4/vc4_plane.c static void vc4_write_tpz(struct vc4_plane_state *vc4_state, u32 src, u32 dst)
vc4_state         405 drivers/gpu/drm/vc4/vc4_plane.c 	vc4_dlist_write(vc4_state,
vc4_state         408 drivers/gpu/drm/vc4/vc4_plane.c 	vc4_dlist_write(vc4_state,
vc4_state         412 drivers/gpu/drm/vc4/vc4_plane.c static void vc4_write_ppf(struct vc4_plane_state *vc4_state, u32 src, u32 dst)
vc4_state         416 drivers/gpu/drm/vc4/vc4_plane.c 	vc4_dlist_write(vc4_state,
vc4_state         424 drivers/gpu/drm/vc4/vc4_plane.c 	struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
vc4_state         428 drivers/gpu/drm/vc4/vc4_plane.c 	u32 pix_per_line = max(vc4_state->src_w[0], (u32)vc4_state->crtc_w);
vc4_state         432 drivers/gpu/drm/vc4/vc4_plane.c 	if (vc4_state->y_scaling[0] == VC4_SCALING_NONE &&
vc4_state         433 drivers/gpu/drm/vc4/vc4_plane.c 	    vc4_state->y_scaling[1] == VC4_SCALING_NONE)
vc4_state         436 drivers/gpu/drm/vc4/vc4_plane.c 	if (!vc4_state->is_yuv) {
vc4_state         437 drivers/gpu/drm/vc4/vc4_plane.c 		if (vc4_state->y_scaling[0] == VC4_SCALING_TPZ)
vc4_state         459 drivers/gpu/drm/vc4/vc4_plane.c 	struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
vc4_state         462 drivers/gpu/drm/vc4/vc4_plane.c 	if (vc4_state->x_scaling[channel] == VC4_SCALING_PPF) {
vc4_state         463 drivers/gpu/drm/vc4/vc4_plane.c 		vc4_write_ppf(vc4_state,
vc4_state         464 drivers/gpu/drm/vc4/vc4_plane.c 			      vc4_state->src_w[channel], vc4_state->crtc_w);
vc4_state         468 drivers/gpu/drm/vc4/vc4_plane.c 	if (vc4_state->y_scaling[channel] == VC4_SCALING_PPF) {
vc4_state         469 drivers/gpu/drm/vc4/vc4_plane.c 		vc4_write_ppf(vc4_state,
vc4_state         470 drivers/gpu/drm/vc4/vc4_plane.c 			      vc4_state->src_h[channel], vc4_state->crtc_h);
vc4_state         471 drivers/gpu/drm/vc4/vc4_plane.c 		vc4_dlist_write(vc4_state, 0xc0c0c0c0);
vc4_state         475 drivers/gpu/drm/vc4/vc4_plane.c 	if (vc4_state->x_scaling[channel] == VC4_SCALING_TPZ) {
vc4_state         476 drivers/gpu/drm/vc4/vc4_plane.c 		vc4_write_tpz(vc4_state,
vc4_state         477 drivers/gpu/drm/vc4/vc4_plane.c 			      vc4_state->src_w[channel], vc4_state->crtc_w);
vc4_state         481 drivers/gpu/drm/vc4/vc4_plane.c 	if (vc4_state->y_scaling[channel] == VC4_SCALING_TPZ) {
vc4_state         482 drivers/gpu/drm/vc4/vc4_plane.c 		vc4_write_tpz(vc4_state,
vc4_state         483 drivers/gpu/drm/vc4/vc4_plane.c 			      vc4_state->src_h[channel], vc4_state->crtc_h);
vc4_state         484 drivers/gpu/drm/vc4/vc4_plane.c 		vc4_dlist_write(vc4_state, 0xc0c0c0c0);
vc4_state         492 drivers/gpu/drm/vc4/vc4_plane.c 	struct vc4_plane_state *vc4_state;
vc4_state         496 drivers/gpu/drm/vc4/vc4_plane.c 	vc4_state = to_vc4_plane_state(state);
vc4_state         508 drivers/gpu/drm/vc4/vc4_plane.c 	if (vc4_state->x_scaling[0] != VC4_SCALING_NONE ||
vc4_state         509 drivers/gpu/drm/vc4/vc4_plane.c 	    vc4_state->x_scaling[1] != VC4_SCALING_NONE ||
vc4_state         510 drivers/gpu/drm/vc4/vc4_plane.c 	    vc4_state->y_scaling[0] != VC4_SCALING_NONE ||
vc4_state         511 drivers/gpu/drm/vc4/vc4_plane.c 	    vc4_state->y_scaling[1] != VC4_SCALING_NONE)
vc4_state         516 drivers/gpu/drm/vc4/vc4_plane.c 	vc4_state->membus_load = 0;
vc4_state         517 drivers/gpu/drm/vc4/vc4_plane.c 	vc4_state->hvs_load = 0;
vc4_state         530 drivers/gpu/drm/vc4/vc4_plane.c 		vscale_factor = DIV_ROUND_UP(vc4_state->src_h[i],
vc4_state         531 drivers/gpu/drm/vc4/vc4_plane.c 					     vc4_state->crtc_h);
vc4_state         532 drivers/gpu/drm/vc4/vc4_plane.c 		vc4_state->membus_load += vc4_state->src_w[i] *
vc4_state         533 drivers/gpu/drm/vc4/vc4_plane.c 					  vc4_state->src_h[i] * vscale_factor *
vc4_state         535 drivers/gpu/drm/vc4/vc4_plane.c 		vc4_state->hvs_load += vc4_state->crtc_h * vc4_state->crtc_w;
vc4_state         538 drivers/gpu/drm/vc4/vc4_plane.c 	vc4_state->hvs_load *= vrefresh;
vc4_state         539 drivers/gpu/drm/vc4/vc4_plane.c 	vc4_state->hvs_load >>= hvs_load_shift;
vc4_state         540 drivers/gpu/drm/vc4/vc4_plane.c 	vc4_state->membus_load *= vrefresh;
vc4_state         546 drivers/gpu/drm/vc4/vc4_plane.c 	struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
vc4_state         554 drivers/gpu/drm/vc4/vc4_plane.c 	if (WARN_ON(!vc4_state->lbm_offset))
vc4_state         560 drivers/gpu/drm/vc4/vc4_plane.c 	if (!vc4_state->lbm.allocated) {
vc4_state         565 drivers/gpu/drm/vc4/vc4_plane.c 						 &vc4_state->lbm,
vc4_state         572 drivers/gpu/drm/vc4/vc4_plane.c 		WARN_ON_ONCE(lbm_size != vc4_state->lbm.size);
vc4_state         575 drivers/gpu/drm/vc4/vc4_plane.c 	vc4_state->dlist[vc4_state->lbm_offset] = vc4_state->lbm.start;
vc4_state         587 drivers/gpu/drm/vc4/vc4_plane.c 	struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
vc4_state         589 drivers/gpu/drm/vc4/vc4_plane.c 	u32 ctl0_offset = vc4_state->dlist_count;
vc4_state         603 drivers/gpu/drm/vc4/vc4_plane.c 	if (vc4_state->dlist_initialized)
vc4_state         630 drivers/gpu/drm/vc4/vc4_plane.c 	src_y = vc4_state->src_y;
vc4_state         632 drivers/gpu/drm/vc4/vc4_plane.c 		src_y += vc4_state->src_h[0] - 1;
vc4_state         643 drivers/gpu/drm/vc4/vc4_plane.c 			vc4_state->offsets[i] += src_y /
vc4_state         647 drivers/gpu/drm/vc4/vc4_plane.c 			vc4_state->offsets[i] += vc4_state->src_x /
vc4_state         670 drivers/gpu/drm/vc4/vc4_plane.c 		u32 tiles_l = vc4_state->src_x >> tile_w_shift;
vc4_state         680 drivers/gpu/drm/vc4/vc4_plane.c 		u32 x_off = vc4_state->src_x & tile_w_mask;
vc4_state         704 drivers/gpu/drm/vc4/vc4_plane.c 		vc4_state->offsets[0] += tiles_t * (tiles_w << tile_size_shift);
vc4_state         705 drivers/gpu/drm/vc4/vc4_plane.c 		vc4_state->offsets[0] += subtile_y << 8;
vc4_state         706 drivers/gpu/drm/vc4/vc4_plane.c 		vc4_state->offsets[0] += utile_y << 4;
vc4_state         711 drivers/gpu/drm/vc4/vc4_plane.c 			vc4_state->offsets[0] += (tiles_w - tiles_l) <<
vc4_state         713 drivers/gpu/drm/vc4/vc4_plane.c 			vc4_state->offsets[0] -= (1 + !tile_y) << 10;
vc4_state         715 drivers/gpu/drm/vc4/vc4_plane.c 			vc4_state->offsets[0] += tiles_l << tile_size_shift;
vc4_state         716 drivers/gpu/drm/vc4/vc4_plane.c 			vc4_state->offsets[0] += tile_y << 10;
vc4_state         753 drivers/gpu/drm/vc4/vc4_plane.c 		tile = vc4_state->src_x / pix_per_tile;
vc4_state         754 drivers/gpu/drm/vc4/vc4_plane.c 		x_off = vc4_state->src_x % pix_per_tile;
vc4_state         760 drivers/gpu/drm/vc4/vc4_plane.c 			vc4_state->offsets[i] += param * tile_w * tile;
vc4_state         761 drivers/gpu/drm/vc4/vc4_plane.c 			vc4_state->offsets[i] += src_y /
vc4_state         764 drivers/gpu/drm/vc4/vc4_plane.c 			vc4_state->offsets[i] += x_off /
vc4_state         780 drivers/gpu/drm/vc4/vc4_plane.c 	vc4_dlist_write(vc4_state,
vc4_state         788 drivers/gpu/drm/vc4/vc4_plane.c 			(vc4_state->is_unity ? SCALER_CTL0_UNITY : 0) |
vc4_state         793 drivers/gpu/drm/vc4/vc4_plane.c 	vc4_state->pos0_offset = vc4_state->dlist_count;
vc4_state         794 drivers/gpu/drm/vc4/vc4_plane.c 	vc4_dlist_write(vc4_state,
vc4_state         796 drivers/gpu/drm/vc4/vc4_plane.c 			VC4_SET_FIELD(vc4_state->crtc_x, SCALER_POS0_START_X) |
vc4_state         797 drivers/gpu/drm/vc4/vc4_plane.c 			VC4_SET_FIELD(vc4_state->crtc_y, SCALER_POS0_START_Y));
vc4_state         800 drivers/gpu/drm/vc4/vc4_plane.c 	if (!vc4_state->is_unity) {
vc4_state         801 drivers/gpu/drm/vc4/vc4_plane.c 		vc4_dlist_write(vc4_state,
vc4_state         802 drivers/gpu/drm/vc4/vc4_plane.c 				VC4_SET_FIELD(vc4_state->crtc_w,
vc4_state         804 drivers/gpu/drm/vc4/vc4_plane.c 				VC4_SET_FIELD(vc4_state->crtc_h,
vc4_state         816 drivers/gpu/drm/vc4/vc4_plane.c 	vc4_state->pos2_offset = vc4_state->dlist_count;
vc4_state         817 drivers/gpu/drm/vc4/vc4_plane.c 	vc4_dlist_write(vc4_state,
vc4_state         824 drivers/gpu/drm/vc4/vc4_plane.c 			VC4_SET_FIELD(vc4_state->src_w[0], SCALER_POS2_WIDTH) |
vc4_state         825 drivers/gpu/drm/vc4/vc4_plane.c 			VC4_SET_FIELD(vc4_state->src_h[0], SCALER_POS2_HEIGHT));
vc4_state         828 drivers/gpu/drm/vc4/vc4_plane.c 	vc4_dlist_write(vc4_state, 0xc0c0c0c0);
vc4_state         835 drivers/gpu/drm/vc4/vc4_plane.c 	vc4_state->ptr0_offset = vc4_state->dlist_count;
vc4_state         837 drivers/gpu/drm/vc4/vc4_plane.c 		vc4_dlist_write(vc4_state, vc4_state->offsets[i]);
vc4_state         841 drivers/gpu/drm/vc4/vc4_plane.c 		vc4_dlist_write(vc4_state, 0xc0c0c0c0);
vc4_state         844 drivers/gpu/drm/vc4/vc4_plane.c 	vc4_dlist_write(vc4_state, pitch0);
vc4_state         849 drivers/gpu/drm/vc4/vc4_plane.c 			vc4_dlist_write(vc4_state,
vc4_state         853 drivers/gpu/drm/vc4/vc4_plane.c 			vc4_dlist_write(vc4_state, pitch0);
vc4_state         858 drivers/gpu/drm/vc4/vc4_plane.c 	if (vc4_state->is_yuv) {
vc4_state         859 drivers/gpu/drm/vc4/vc4_plane.c 		vc4_dlist_write(vc4_state, SCALER_CSC0_ITR_R_601_5);
vc4_state         860 drivers/gpu/drm/vc4/vc4_plane.c 		vc4_dlist_write(vc4_state, SCALER_CSC1_ITR_R_601_5);
vc4_state         861 drivers/gpu/drm/vc4/vc4_plane.c 		vc4_dlist_write(vc4_state, SCALER_CSC2_ITR_R_601_5);
vc4_state         864 drivers/gpu/drm/vc4/vc4_plane.c 	vc4_state->lbm_offset = 0;
vc4_state         866 drivers/gpu/drm/vc4/vc4_plane.c 	if (vc4_state->x_scaling[0] != VC4_SCALING_NONE ||
vc4_state         867 drivers/gpu/drm/vc4/vc4_plane.c 	    vc4_state->x_scaling[1] != VC4_SCALING_NONE ||
vc4_state         868 drivers/gpu/drm/vc4/vc4_plane.c 	    vc4_state->y_scaling[0] != VC4_SCALING_NONE ||
vc4_state         869 drivers/gpu/drm/vc4/vc4_plane.c 	    vc4_state->y_scaling[1] != VC4_SCALING_NONE) {
vc4_state         873 drivers/gpu/drm/vc4/vc4_plane.c 		if (vc4_state->y_scaling[0] != VC4_SCALING_NONE ||
vc4_state         874 drivers/gpu/drm/vc4/vc4_plane.c 		    vc4_state->y_scaling[1] != VC4_SCALING_NONE)
vc4_state         875 drivers/gpu/drm/vc4/vc4_plane.c 			vc4_state->lbm_offset = vc4_state->dlist_count++;
vc4_state         889 drivers/gpu/drm/vc4/vc4_plane.c 		if (vc4_state->x_scaling[0] == VC4_SCALING_PPF ||
vc4_state         890 drivers/gpu/drm/vc4/vc4_plane.c 		    vc4_state->y_scaling[0] == VC4_SCALING_PPF ||
vc4_state         891 drivers/gpu/drm/vc4/vc4_plane.c 		    vc4_state->x_scaling[1] == VC4_SCALING_PPF ||
vc4_state         892 drivers/gpu/drm/vc4/vc4_plane.c 		    vc4_state->y_scaling[1] == VC4_SCALING_PPF) {
vc4_state         897 drivers/gpu/drm/vc4/vc4_plane.c 			vc4_dlist_write(vc4_state, kernel);
vc4_state         899 drivers/gpu/drm/vc4/vc4_plane.c 			vc4_dlist_write(vc4_state, kernel);
vc4_state         901 drivers/gpu/drm/vc4/vc4_plane.c 			vc4_dlist_write(vc4_state, kernel);
vc4_state         903 drivers/gpu/drm/vc4/vc4_plane.c 			vc4_dlist_write(vc4_state, kernel);
vc4_state         907 drivers/gpu/drm/vc4/vc4_plane.c 	vc4_state->dlist[ctl0_offset] |=
vc4_state         908 drivers/gpu/drm/vc4/vc4_plane.c 		VC4_SET_FIELD(vc4_state->dlist_count, SCALER_CTL0_SIZE);
vc4_state         911 drivers/gpu/drm/vc4/vc4_plane.c 	covers_screen = vc4_state->crtc_x == 0 && vc4_state->crtc_y == 0 &&
vc4_state         912 drivers/gpu/drm/vc4/vc4_plane.c 			vc4_state->crtc_w == state->crtc->mode.hdisplay &&
vc4_state         913 drivers/gpu/drm/vc4/vc4_plane.c 			vc4_state->crtc_h == state->crtc->mode.vdisplay;
vc4_state         918 drivers/gpu/drm/vc4/vc4_plane.c 	vc4_state->needs_bg_fill = fb->format->has_alpha || !covers_screen ||
vc4_state         926 drivers/gpu/drm/vc4/vc4_plane.c 	vc4_state->dlist_initialized = 1;
vc4_state         943 drivers/gpu/drm/vc4/vc4_plane.c 	struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
vc4_state         946 drivers/gpu/drm/vc4/vc4_plane.c 	vc4_state->dlist_count = 0;
vc4_state         970 drivers/gpu/drm/vc4/vc4_plane.c 	struct vc4_plane_state *vc4_state = to_vc4_plane_state(plane->state);
vc4_state         973 drivers/gpu/drm/vc4/vc4_plane.c 	vc4_state->hw_dlist = dlist;
vc4_state         976 drivers/gpu/drm/vc4/vc4_plane.c 	for (i = 0; i < vc4_state->dlist_count; i++)
vc4_state         977 drivers/gpu/drm/vc4/vc4_plane.c 		writel(vc4_state->dlist[i], &dlist[i]);
vc4_state         979 drivers/gpu/drm/vc4/vc4_plane.c 	return vc4_state->dlist_count;
vc4_state         984 drivers/gpu/drm/vc4/vc4_plane.c 	const struct vc4_plane_state *vc4_state =
vc4_state         985 drivers/gpu/drm/vc4/vc4_plane.c 		container_of(state, typeof(*vc4_state), base);
vc4_state         987 drivers/gpu/drm/vc4/vc4_plane.c 	return vc4_state->dlist_count;
vc4_state         995 drivers/gpu/drm/vc4/vc4_plane.c 	struct vc4_plane_state *vc4_state = to_vc4_plane_state(plane->state);
vc4_state        1009 drivers/gpu/drm/vc4/vc4_plane.c 	writel(addr, &vc4_state->hw_dlist[vc4_state->ptr0_offset]);
vc4_state        1015 drivers/gpu/drm/vc4/vc4_plane.c 	vc4_state->dlist[vc4_state->ptr0_offset] = addr;
vc4_state        1021 drivers/gpu/drm/vc4/vc4_plane.c 	struct vc4_plane_state *vc4_state, *new_vc4_state;
vc4_state        1045 drivers/gpu/drm/vc4/vc4_plane.c 	vc4_state = to_vc4_plane_state(plane->state);
vc4_state        1047 drivers/gpu/drm/vc4/vc4_plane.c 	vc4_state->crtc_x = new_vc4_state->crtc_x;
vc4_state        1048 drivers/gpu/drm/vc4/vc4_plane.c 	vc4_state->crtc_y = new_vc4_state->crtc_y;
vc4_state        1049 drivers/gpu/drm/vc4/vc4_plane.c 	vc4_state->crtc_h = new_vc4_state->crtc_h;
vc4_state        1050 drivers/gpu/drm/vc4/vc4_plane.c 	vc4_state->crtc_w = new_vc4_state->crtc_w;
vc4_state        1051 drivers/gpu/drm/vc4/vc4_plane.c 	vc4_state->src_x = new_vc4_state->src_x;
vc4_state        1052 drivers/gpu/drm/vc4/vc4_plane.c 	vc4_state->src_y = new_vc4_state->src_y;
vc4_state        1053 drivers/gpu/drm/vc4/vc4_plane.c 	memcpy(vc4_state->src_w, new_vc4_state->src_w,
vc4_state        1054 drivers/gpu/drm/vc4/vc4_plane.c 	       sizeof(vc4_state->src_w));
vc4_state        1055 drivers/gpu/drm/vc4/vc4_plane.c 	memcpy(vc4_state->src_h, new_vc4_state->src_h,
vc4_state        1056 drivers/gpu/drm/vc4/vc4_plane.c 	       sizeof(vc4_state->src_h));
vc4_state        1057 drivers/gpu/drm/vc4/vc4_plane.c 	memcpy(vc4_state->x_scaling, new_vc4_state->x_scaling,
vc4_state        1058 drivers/gpu/drm/vc4/vc4_plane.c 	       sizeof(vc4_state->x_scaling));
vc4_state        1059 drivers/gpu/drm/vc4/vc4_plane.c 	memcpy(vc4_state->y_scaling, new_vc4_state->y_scaling,
vc4_state        1060 drivers/gpu/drm/vc4/vc4_plane.c 	       sizeof(vc4_state->y_scaling));
vc4_state        1061 drivers/gpu/drm/vc4/vc4_plane.c 	vc4_state->is_unity = new_vc4_state->is_unity;
vc4_state        1062 drivers/gpu/drm/vc4/vc4_plane.c 	vc4_state->is_yuv = new_vc4_state->is_yuv;
vc4_state        1063 drivers/gpu/drm/vc4/vc4_plane.c 	memcpy(vc4_state->offsets, new_vc4_state->offsets,
vc4_state        1064 drivers/gpu/drm/vc4/vc4_plane.c 	       sizeof(vc4_state->offsets));
vc4_state        1065 drivers/gpu/drm/vc4/vc4_plane.c 	vc4_state->needs_bg_fill = new_vc4_state->needs_bg_fill;
vc4_state        1068 drivers/gpu/drm/vc4/vc4_plane.c 	vc4_state->dlist[vc4_state->pos0_offset] =
vc4_state        1069 drivers/gpu/drm/vc4/vc4_plane.c 		new_vc4_state->dlist[vc4_state->pos0_offset];
vc4_state        1070 drivers/gpu/drm/vc4/vc4_plane.c 	vc4_state->dlist[vc4_state->pos2_offset] =
vc4_state        1071 drivers/gpu/drm/vc4/vc4_plane.c 		new_vc4_state->dlist[vc4_state->pos2_offset];
vc4_state        1072 drivers/gpu/drm/vc4/vc4_plane.c 	vc4_state->dlist[vc4_state->ptr0_offset] =
vc4_state        1073 drivers/gpu/drm/vc4/vc4_plane.c 		new_vc4_state->dlist[vc4_state->ptr0_offset];
vc4_state        1079 drivers/gpu/drm/vc4/vc4_plane.c 	writel(vc4_state->dlist[vc4_state->pos0_offset],
vc4_state        1080 drivers/gpu/drm/vc4/vc4_plane.c 	       &vc4_state->hw_dlist[vc4_state->pos0_offset]);
vc4_state        1081 drivers/gpu/drm/vc4/vc4_plane.c 	writel(vc4_state->dlist[vc4_state->pos2_offset],
vc4_state        1082 drivers/gpu/drm/vc4/vc4_plane.c 	       &vc4_state->hw_dlist[vc4_state->pos2_offset]);
vc4_state        1083 drivers/gpu/drm/vc4/vc4_plane.c 	writel(vc4_state->dlist[vc4_state->ptr0_offset],
vc4_state        1084 drivers/gpu/drm/vc4/vc4_plane.c 	       &vc4_state->hw_dlist[vc4_state->ptr0_offset]);