validation_state 156 drivers/gpu/drm/vc4/vc4_validate_shaders.c struct vc4_shader_validation_state *validation_state, validation_state 170 drivers/gpu/drm/vc4/vc4_validate_shaders.c &validation_state->tmu_setup[tmu], validation_state 177 drivers/gpu/drm/vc4/vc4_validate_shaders.c validation_state->tmu_setup[tmu].p_offset[i] = ~0; validation_state 184 drivers/gpu/drm/vc4/vc4_validate_shaders.c struct vc4_shader_validation_state *validation_state, validation_state 187 drivers/gpu/drm/vc4/vc4_validate_shaders.c uint64_t inst = validation_state->shader[validation_state->ip]; validation_state 195 drivers/gpu/drm/vc4/vc4_validate_shaders.c bool is_direct = submit && validation_state->tmu_write_count[tmu] == 0; validation_state 227 drivers/gpu/drm/vc4/vc4_validate_shaders.c clamp_offset = validation_state->live_min_clamp_offsets[clamp_reg]; validation_state 236 drivers/gpu/drm/vc4/vc4_validate_shaders.c validation_state->tmu_setup[tmu].p_offset[1] = validation_state 245 drivers/gpu/drm/vc4/vc4_validate_shaders.c validation_state->tmu_setup[tmu].is_direct = true; validation_state 255 drivers/gpu/drm/vc4/vc4_validate_shaders.c if (validation_state->tmu_write_count[tmu] >= 4) { validation_state 260 drivers/gpu/drm/vc4/vc4_validate_shaders.c validation_state->tmu_setup[tmu].p_offset[validation_state->tmu_write_count[tmu]] = validation_state 262 drivers/gpu/drm/vc4/vc4_validate_shaders.c validation_state->tmu_write_count[tmu]++; validation_state 267 drivers/gpu/drm/vc4/vc4_validate_shaders.c if (validation_state->needs_uniform_address_update) { validation_state 277 drivers/gpu/drm/vc4/vc4_validate_shaders.c validation_state, tmu)) { validation_state 281 drivers/gpu/drm/vc4/vc4_validate_shaders.c validation_state->tmu_write_count[tmu] = 0; validation_state 308 drivers/gpu/drm/vc4/vc4_validate_shaders.c struct vc4_shader_validation_state *validation_state, validation_state 311 drivers/gpu/drm/vc4/vc4_validate_shaders.c uint64_t inst = validation_state->shader[validation_state->ip]; validation_state 366 drivers/gpu/drm/vc4/vc4_validate_shaders.c if (validation_state->live_immediates[add_lri] != expected_offset) { validation_state 368 drivers/gpu/drm/vc4/vc4_validate_shaders.c validation_state->live_immediates[add_lri], validation_state 380 drivers/gpu/drm/vc4/vc4_validate_shaders.c validation_state->needs_uniform_address_update = false; validation_state 381 drivers/gpu/drm/vc4/vc4_validate_shaders.c validation_state->needs_uniform_address_for_loop = false; validation_state 387 drivers/gpu/drm/vc4/vc4_validate_shaders.c struct vc4_shader_validation_state *validation_state, validation_state 390 drivers/gpu/drm/vc4/vc4_validate_shaders.c uint64_t inst = validation_state->shader[validation_state->ip]; validation_state 407 drivers/gpu/drm/vc4/vc4_validate_shaders.c validation_state->live_immediates[lri] = validation_state 410 drivers/gpu/drm/vc4/vc4_validate_shaders.c validation_state->live_immediates[lri] = ~0; validation_state 414 drivers/gpu/drm/vc4/vc4_validate_shaders.c validation_state->all_registers_used = true; validation_state 426 drivers/gpu/drm/vc4/vc4_validate_shaders.c validation_state, validation_state 445 drivers/gpu/drm/vc4/vc4_validate_shaders.c return check_tmu_write(validated_shader, validation_state, validation_state 479 drivers/gpu/drm/vc4/vc4_validate_shaders.c struct vc4_shader_validation_state *validation_state) validation_state 481 drivers/gpu/drm/vc4/vc4_validate_shaders.c uint64_t inst = validation_state->shader[validation_state->ip]; validation_state 500 drivers/gpu/drm/vc4/vc4_validate_shaders.c validation_state->live_max_clamp_regs[lri_add_a]); validation_state 506 drivers/gpu/drm/vc4/vc4_validate_shaders.c validation_state->live_max_clamp_regs[lri_mul] = false; validation_state 507 drivers/gpu/drm/vc4/vc4_validate_shaders.c validation_state->live_min_clamp_offsets[lri_mul] = ~0; validation_state 510 drivers/gpu/drm/vc4/vc4_validate_shaders.c validation_state->live_max_clamp_regs[lri_add] = false; validation_state 511 drivers/gpu/drm/vc4/vc4_validate_shaders.c validation_state->live_min_clamp_offsets[lri_add] = ~0; validation_state 533 drivers/gpu/drm/vc4/vc4_validate_shaders.c validation_state->live_max_clamp_regs[lri_add] = true; validation_state 547 drivers/gpu/drm/vc4/vc4_validate_shaders.c validation_state->live_min_clamp_offsets[lri_add] = validation_state 554 drivers/gpu/drm/vc4/vc4_validate_shaders.c struct vc4_shader_validation_state *validation_state) validation_state 556 drivers/gpu/drm/vc4/vc4_validate_shaders.c uint64_t inst = validation_state->shader[validation_state->ip]; validation_state 566 drivers/gpu/drm/vc4/vc4_validate_shaders.c ok = (check_reg_write(validated_shader, validation_state, false) && validation_state 567 drivers/gpu/drm/vc4/vc4_validate_shaders.c check_reg_write(validated_shader, validation_state, true)); validation_state 569 drivers/gpu/drm/vc4/vc4_validate_shaders.c track_live_clamps(validated_shader, validation_state); validation_state 577 drivers/gpu/drm/vc4/vc4_validate_shaders.c struct vc4_shader_validation_state *validation_state, validation_state 585 drivers/gpu/drm/vc4/vc4_validate_shaders.c validation_state->needs_uniform_address_for_loop = true; validation_state 592 drivers/gpu/drm/vc4/vc4_validate_shaders.c validation_state->ip); validation_state 601 drivers/gpu/drm/vc4/vc4_validate_shaders.c struct vc4_shader_validation_state *validation_state) validation_state 603 drivers/gpu/drm/vc4/vc4_validate_shaders.c uint64_t inst = validation_state->shader[validation_state->ip]; validation_state 616 drivers/gpu/drm/vc4/vc4_validate_shaders.c if (validation_state->needs_uniform_address_update) { validation_state 625 drivers/gpu/drm/vc4/vc4_validate_shaders.c validation_state->all_registers_used = true; validation_state 635 drivers/gpu/drm/vc4/vc4_validate_shaders.c vc4_validate_branches(struct vc4_shader_validation_state *validation_state) validation_state 641 drivers/gpu/drm/vc4/vc4_validate_shaders.c for (ip = 0; ip < validation_state->max_ip; ip++) { validation_state 642 drivers/gpu/drm/vc4/vc4_validate_shaders.c uint64_t inst = validation_state->shader[ip]; validation_state 655 drivers/gpu/drm/vc4/vc4_validate_shaders.c validation_state->max_ip = ip + 3; validation_state 690 drivers/gpu/drm/vc4/vc4_validate_shaders.c if (branch_target_ip >= validation_state->max_ip) { validation_state 693 drivers/gpu/drm/vc4/vc4_validate_shaders.c validation_state->max_ip); validation_state 696 drivers/gpu/drm/vc4/vc4_validate_shaders.c set_bit(branch_target_ip, validation_state->branch_targets); validation_state 701 drivers/gpu/drm/vc4/vc4_validate_shaders.c if (after_delay_ip >= validation_state->max_ip) { validation_state 704 drivers/gpu/drm/vc4/vc4_validate_shaders.c ip, after_delay_ip, validation_state->max_ip); validation_state 707 drivers/gpu/drm/vc4/vc4_validate_shaders.c set_bit(after_delay_ip, validation_state->branch_targets); validation_state 711 drivers/gpu/drm/vc4/vc4_validate_shaders.c if (max_branch_target > validation_state->max_ip - 3) { validation_state 723 drivers/gpu/drm/vc4/vc4_validate_shaders.c reset_validation_state(struct vc4_shader_validation_state *validation_state) validation_state 728 drivers/gpu/drm/vc4/vc4_validate_shaders.c validation_state->tmu_setup[i / 4].p_offset[i % 4] = ~0; validation_state 731 drivers/gpu/drm/vc4/vc4_validate_shaders.c validation_state->live_min_clamp_offsets[i] = ~0; validation_state 732 drivers/gpu/drm/vc4/vc4_validate_shaders.c validation_state->live_max_clamp_regs[i] = false; validation_state 733 drivers/gpu/drm/vc4/vc4_validate_shaders.c validation_state->live_immediates[i] = ~0; validation_state 738 drivers/gpu/drm/vc4/vc4_validate_shaders.c texturing_in_progress(struct vc4_shader_validation_state *validation_state) validation_state 740 drivers/gpu/drm/vc4/vc4_validate_shaders.c return (validation_state->tmu_write_count[0] != 0 || validation_state 741 drivers/gpu/drm/vc4/vc4_validate_shaders.c validation_state->tmu_write_count[1] != 0); validation_state 745 drivers/gpu/drm/vc4/vc4_validate_shaders.c vc4_handle_branch_target(struct vc4_shader_validation_state *validation_state) validation_state 747 drivers/gpu/drm/vc4/vc4_validate_shaders.c uint32_t ip = validation_state->ip; validation_state 749 drivers/gpu/drm/vc4/vc4_validate_shaders.c if (!test_bit(ip, validation_state->branch_targets)) validation_state 752 drivers/gpu/drm/vc4/vc4_validate_shaders.c if (texturing_in_progress(validation_state)) { validation_state 764 drivers/gpu/drm/vc4/vc4_validate_shaders.c reset_validation_state(validation_state); validation_state 773 drivers/gpu/drm/vc4/vc4_validate_shaders.c validation_state->needs_uniform_address_update = true; validation_state 786 drivers/gpu/drm/vc4/vc4_validate_shaders.c struct vc4_shader_validation_state validation_state; validation_state 788 drivers/gpu/drm/vc4/vc4_validate_shaders.c memset(&validation_state, 0, sizeof(validation_state)); validation_state 789 drivers/gpu/drm/vc4/vc4_validate_shaders.c validation_state.shader = shader_obj->vaddr; validation_state 790 drivers/gpu/drm/vc4/vc4_validate_shaders.c validation_state.max_ip = shader_obj->base.size / sizeof(uint64_t); validation_state 792 drivers/gpu/drm/vc4/vc4_validate_shaders.c reset_validation_state(&validation_state); validation_state 794 drivers/gpu/drm/vc4/vc4_validate_shaders.c validation_state.branch_targets = validation_state 795 drivers/gpu/drm/vc4/vc4_validate_shaders.c kcalloc(BITS_TO_LONGS(validation_state.max_ip), validation_state 797 drivers/gpu/drm/vc4/vc4_validate_shaders.c if (!validation_state.branch_targets) validation_state 804 drivers/gpu/drm/vc4/vc4_validate_shaders.c if (!vc4_validate_branches(&validation_state)) validation_state 807 drivers/gpu/drm/vc4/vc4_validate_shaders.c for (ip = 0; ip < validation_state.max_ip; ip++) { validation_state 808 drivers/gpu/drm/vc4/vc4_validate_shaders.c uint64_t inst = validation_state.shader[ip]; validation_state 811 drivers/gpu/drm/vc4/vc4_validate_shaders.c validation_state.ip = ip; validation_state 813 drivers/gpu/drm/vc4/vc4_validate_shaders.c if (!vc4_handle_branch_target(&validation_state)) validation_state 821 drivers/gpu/drm/vc4/vc4_validate_shaders.c validation_state.live_min_clamp_offsets[i] = ~0; validation_state 822 drivers/gpu/drm/vc4/vc4_validate_shaders.c validation_state.live_max_clamp_regs[i] = false; validation_state 823 drivers/gpu/drm/vc4/vc4_validate_shaders.c validation_state.live_immediates[i] = ~0; validation_state 839 drivers/gpu/drm/vc4/vc4_validate_shaders.c &validation_state)) { validation_state 845 drivers/gpu/drm/vc4/vc4_validate_shaders.c &validation_state)) validation_state 869 drivers/gpu/drm/vc4/vc4_validate_shaders.c &validation_state)) { validation_state 877 drivers/gpu/drm/vc4/vc4_validate_shaders.c &validation_state, ip)) validation_state 900 drivers/gpu/drm/vc4/vc4_validate_shaders.c if (ip == validation_state.max_ip) { validation_state 909 drivers/gpu/drm/vc4/vc4_validate_shaders.c validation_state.all_registers_used) { validation_state 924 drivers/gpu/drm/vc4/vc4_validate_shaders.c if (validation_state.needs_uniform_address_for_loop) { validation_state 938 drivers/gpu/drm/vc4/vc4_validate_shaders.c kfree(validation_state.branch_targets); validation_state 943 drivers/gpu/drm/vc4/vc4_validate_shaders.c kfree(validation_state.branch_targets);