UvdLevel          963 drivers/gpu/drm/amd/amdgpu/kv_dpm.c 				   offsetof(SMU7_Fusion_DpmTable, UvdLevel),
UvdLevel          270 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h 	SMU72_Discrete_UvdLevel             UvdLevel[SMU72_MAX_LEVELS_UVD];
UvdLevel          254 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h     SMU73_Discrete_UvdLevel             UvdLevel                [SMU73_MAX_LEVELS_UVD];
UvdLevel          286 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h 	SMU74_Discrete_UvdLevel             UvdLevel[SMU74_MAX_LEVELS_UVD];
UvdLevel          292 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h 	SMU75_Discrete_UvdLevel             UvdLevel                [SMU75_MAX_LEVELS_UVD];
UvdLevel          328 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h     SMU7_Discrete_UvdLevel              UvdLevel                [SMU7_MAX_LEVELS_UVD];
UvdLevel          235 drivers/gpu/drm/amd/powerplay/inc/smu7_fusion.h     SMU7_Fusion_UvdLevel              UvdLevel                [SMU7_MAX_LEVELS_UVD];
UvdLevel         1528 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		table->UvdLevel[count].VclkFrequency =
UvdLevel         1530 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		table->UvdLevel[count].DclkFrequency =
UvdLevel         1532 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		table->UvdLevel[count].MinVddc =
UvdLevel         1534 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		table->UvdLevel[count].MinVddcPhases = 1;
UvdLevel         1537 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 				table->UvdLevel[count].VclkFrequency, &dividers);
UvdLevel         1541 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
UvdLevel         1544 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 				table->UvdLevel[count].DclkFrequency, &dividers);
UvdLevel         1548 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;
UvdLevel         1549 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency);
UvdLevel         1550 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency);
UvdLevel         1551 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		CONVERT_FROM_HOST_TO_SMC_US(table->UvdLevel[count].MinVddc);
UvdLevel         1573 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		table->UvdLevel[count].MinVoltage = 0;
UvdLevel         1574 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk;
UvdLevel         1575 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk;
UvdLevel         1576 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		table->UvdLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
UvdLevel         1578 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		table->UvdLevel[count].MinVoltage |= ((mm_table->entries[count].vddc -
UvdLevel         1580 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		table->UvdLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
UvdLevel         1584 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 				table->UvdLevel[count].VclkFrequency, &dividers);
UvdLevel         1588 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
UvdLevel         1591 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 				table->UvdLevel[count].DclkFrequency, &dividers);
UvdLevel         1595 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;
UvdLevel         1597 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency);
UvdLevel         1598 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency);
UvdLevel         1599 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].MinVoltage);
UvdLevel         1409 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		table->UvdLevel[count].MinVoltage = 0;
UvdLevel         1410 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk;
UvdLevel         1411 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk;
UvdLevel         1412 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		table->UvdLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
UvdLevel         1423 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		table->UvdLevel[count].MinVoltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
UvdLevel         1424 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		table->UvdLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
UvdLevel         1428 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 				table->UvdLevel[count].VclkFrequency, &dividers);
UvdLevel         1432 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
UvdLevel         1435 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 				table->UvdLevel[count].DclkFrequency, &dividers);
UvdLevel         1439 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;
UvdLevel         1441 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency);
UvdLevel         1442 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency);
UvdLevel         1443 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].MinVoltage);
UvdLevel         1324 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk;
UvdLevel         1325 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk;
UvdLevel         1326 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		table->UvdLevel[count].MinVoltage.Vddc =
UvdLevel         1329 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		table->UvdLevel[count].MinVoltage.VddGfx =
UvdLevel         1333 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		table->UvdLevel[count].MinVoltage.Vddci =
UvdLevel         1336 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		table->UvdLevel[count].MinVoltage.Phases = 1;
UvdLevel         1341 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 					table->UvdLevel[count].VclkFrequency,
UvdLevel         1348 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
UvdLevel         1351 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 							  table->UvdLevel[count].DclkFrequency, &dividers);
UvdLevel         1356 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		table->UvdLevel[count].DclkDivider =
UvdLevel         1359 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency);
UvdLevel         1360 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency);
UvdLevel         1333 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		table->UvdLevel[count].MinVoltage = 0;
UvdLevel         1334 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk;
UvdLevel         1335 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk;
UvdLevel         1336 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		table->UvdLevel[count].MinVoltage |=
UvdLevel         1347 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		table->UvdLevel[count].MinVoltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
UvdLevel         1348 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		table->UvdLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
UvdLevel         1352 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 				table->UvdLevel[count].VclkFrequency, &dividers);
UvdLevel         1356 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
UvdLevel         1359 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 				table->UvdLevel[count].DclkFrequency, &dividers);
UvdLevel         1363 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;
UvdLevel         1365 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency);
UvdLevel         1366 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency);
UvdLevel         1367 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].MinVoltage);
UvdLevel         2659 drivers/gpu/drm/radeon/ci_dpm.c 		table->UvdLevel[count].VclkFrequency =
UvdLevel         2661 drivers/gpu/drm/radeon/ci_dpm.c 		table->UvdLevel[count].DclkFrequency =
UvdLevel         2663 drivers/gpu/drm/radeon/ci_dpm.c 		table->UvdLevel[count].MinVddc =
UvdLevel         2665 drivers/gpu/drm/radeon/ci_dpm.c 		table->UvdLevel[count].MinVddcPhases = 1;
UvdLevel         2669 drivers/gpu/drm/radeon/ci_dpm.c 						     table->UvdLevel[count].VclkFrequency, false, &dividers);
UvdLevel         2673 drivers/gpu/drm/radeon/ci_dpm.c 		table->UvdLevel[count].VclkDivider = (u8)dividers.post_divider;
UvdLevel         2677 drivers/gpu/drm/radeon/ci_dpm.c 						     table->UvdLevel[count].DclkFrequency, false, &dividers);
UvdLevel         2681 drivers/gpu/drm/radeon/ci_dpm.c 		table->UvdLevel[count].DclkDivider = (u8)dividers.post_divider;
UvdLevel         2683 drivers/gpu/drm/radeon/ci_dpm.c 		table->UvdLevel[count].VclkFrequency = cpu_to_be32(table->UvdLevel[count].VclkFrequency);
UvdLevel         2684 drivers/gpu/drm/radeon/ci_dpm.c 		table->UvdLevel[count].DclkFrequency = cpu_to_be32(table->UvdLevel[count].DclkFrequency);
UvdLevel         2685 drivers/gpu/drm/radeon/ci_dpm.c 		table->UvdLevel[count].MinVddc = cpu_to_be16(table->UvdLevel[count].MinVddc);
UvdLevel          881 drivers/gpu/drm/radeon/kv_dpm.c 				   offsetof(SMU7_Fusion_DpmTable, UvdLevel),
UvdLevel          327 drivers/gpu/drm/radeon/smu7_discrete.h     SMU7_Discrete_UvdLevel              UvdLevel                [SMU7_MAX_LEVELS_UVD];
UvdLevel          235 drivers/gpu/drm/radeon/smu7_fusion.h     SMU7_Fusion_UvdLevel              UvdLevel                [SMU7_MAX_LEVELS_UVD];