val0               26 arch/ia64/include/uapi/asm/intrinsics.h #define ia64_native_set_rr0_to_rr4(val0, val1, val2, val3, val4)	\
val0               28 arch/ia64/include/uapi/asm/intrinsics.h 	ia64_native_set_rr(0x0000000000000000UL, (val0));		\
val0              446 arch/mips/include/asm/octeon/cvmx-sriox-defs.h 		uint64_t val0:1;
val0              470 arch/mips/include/asm/octeon/cvmx-sriox-defs.h 		uint64_t val0:1;
val0               52 arch/powerpc/lib/sstep.c extern int do_stq(unsigned long ea, unsigned long val0, unsigned long val1);
val0               54 arch/powerpc/lib/sstep.c extern int do_stqcx(unsigned long ea, unsigned long val0, unsigned long val1,
val0              373 drivers/clk/nxp/clk-lpc32xx.c static inline bool pll_is_valid(u64 val0, u64 val1, u64 min, u64 max)
val0              375 drivers/clk/nxp/clk-lpc32xx.c 	return (val0 >= (val1 * min) && val0 <= (val1 * max));
val0              270 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h 						uint32_t reg0, uint32_t val0,
val0              340 drivers/gpu/drm/mga/mga_drv.h #define DMA_BLOCK(reg0, val0, reg1, val1, reg2, val2, reg3, val3)	\
val0              346 drivers/gpu/drm/mga/mga_drv.h 	DMA_WRITE(1, val0);						\
val0              631 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c 			regs->registers[i] - (regs->val0 >> 2);
val0              665 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c 	if (regs->val0)
val0              666 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c 		in += CRASHDUMP_WRITE(in, regs->val0, regs->val1);
val0              168 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h 	u32 val0;
val0              173 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h 	{ .val0 = _base, .val1 = _type, .registers = _array, \
val0              281 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h 		.val0 = _sel_reg, .val1 = _sel_val }
val0              306 drivers/iio/common/hid-sensors/hid-sensor-attributes.c static void adjust_exponent_nano(int *val0, int *val1, int scale0,
val0              316 drivers/iio/common/hid-sensors/hid-sensor-attributes.c 		*val0 = scale0 * int_pow(10, exp);
val0              328 drivers/iio/common/hid-sensors/hid-sensor-attributes.c 		*val0 += res;
val0              333 drivers/iio/common/hid-sensors/hid-sensor-attributes.c 			*val0 = *val1 = 0;
val0              337 drivers/iio/common/hid-sensors/hid-sensor-attributes.c 		*val0 = scale0 / divisor;
val0              348 drivers/iio/common/hid-sensors/hid-sensor-attributes.c 		*val0 = scale0;
val0              355 drivers/iio/common/hid-sensors/hid-sensor-attributes.c 			int *val0, int *val1)
val0              360 drivers/iio/common/hid-sensors/hid-sensor-attributes.c 	*val0 = 1;
val0              368 drivers/iio/common/hid-sensors/hid-sensor-attributes.c 			adjust_exponent_nano(val0, val1,
val0              483 drivers/iio/common/hid-sensors/hid-sensor-attributes.c 		int val0, val1;
val0              486 drivers/iio/common/hid-sensors/hid-sensor-attributes.c 					&timestamp, &val0, &val1);
val0              487 drivers/iio/common/hid-sensors/hid-sensor-attributes.c 		st->timestamp_ns_scale = val0;
val0             1004 drivers/infiniband/hw/qib/qib_sd7220.c #define RXEQ_VAL(elt, adr, val0, val1, val2, val3) \
val0             1005 drivers/infiniband/hw/qib/qib_sd7220.c 	{RXEQ_INIT_RDESC((elt), (adr)), {(val0), (val1), (val2), (val3)} }
val0             2914 drivers/media/usb/gspca/ov519.c 	unsigned char val0, val1;
val0             2930 drivers/media/usb/gspca/ov519.c 		val0 = *pYTable++;
val0             2932 drivers/media/usb/gspca/ov519.c 		val0 &= 0x0f;
val0             2934 drivers/media/usb/gspca/ov519.c 		val0 |= val1 << 4;
val0             2935 drivers/media/usb/gspca/ov519.c 		reg_w(sd, reg, val0);
val0             2937 drivers/media/usb/gspca/ov519.c 		val0 = *pUVTable++;
val0             2939 drivers/media/usb/gspca/ov519.c 		val0 &= 0x0f;
val0             2941 drivers/media/usb/gspca/ov519.c 		val0 |= val1 << 4;
val0             2942 drivers/media/usb/gspca/ov519.c 		reg_w(sd, reg + size, val0);
val0              870 drivers/misc/sgi-gru/grufault.c 		if (req.val0 < -1 || req.val0 >= GRU_CHIPLETS_PER_HUB ||
val0              876 drivers/misc/sgi-gru/grufault.c 			gts->ts_user_chiplet_id = req.val0;
val0               97 drivers/misc/sgi-gru/grulib.h 	int		val0;
val0              429 drivers/net/ethernet/chelsio/cxgb/pm3393.c 	t1_tpi_read((mac)->adapter, OFFSET(name), &val0);     \
val0              432 drivers/net/ethernet/chelsio/cxgb/pm3393.c 	(mac)->stats.stat_name = (u64)(val0 & 0xffff) | \
val0              446 drivers/net/ethernet/chelsio/cxgb/pm3393.c 	u32	val0, val1, val2, val3;
val0              453 drivers/net/ethernet/chelsio/cxgb/pm3393.c 	pmread(mac, SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_0, &val0);
val0              457 drivers/net/ethernet/chelsio/cxgb/pm3393.c 	ro = ((u64)val0 & 0xffff) | (((u64)val1 & 0xffff) << 16) |
val0              311 drivers/staging/gasket/apex_driver.c 	u32 val0, val1;
val0              363 drivers/staging/gasket/apex_driver.c 		val0 = gasket_dev_read_32(gasket_dev, APEX_BAR_INDEX,
val0              374 drivers/staging/gasket/apex_driver.c 			"Disallow HW clock gating 0x%x -> 0x%x\n", val0, val1);
val0              376 drivers/staging/gasket/apex_driver.c 		val0 = gasket_dev_read_32(gasket_dev, APEX_BAR_INDEX,
val0              386 drivers/staging/gasket/apex_driver.c 			val0, val1);
val0              467 drivers/staging/media/ipu3/ipu3-css.c 		u32 val0 = imgu_css_gdc_lut[0][i] & IMGU_GDC_LUT_MASK;
val0              472 drivers/staging/media/ipu3/ipu3-css.c 		writel(val0 | (val1 << 16),
val0             1735 drivers/thunderbolt/icm.c 	u32 val0, val1;
val0             1753 drivers/thunderbolt/icm.c 	ret = pcie2cio_read(icm, TB_CFG_PORT, port0, PHY_PORT_CS1, &val0);
val0             1760 drivers/thunderbolt/icm.c 	state0 = val0 & PHY_PORT_CS1_LINK_STATE_MASK;
val0             1769 drivers/thunderbolt/icm.c 	val0 |= PHY_PORT_CS1_LINK_DISABLE;
val0             1770 drivers/thunderbolt/icm.c 	ret = pcie2cio_write(icm, TB_CFG_PORT, port0, PHY_PORT_CS1, val0);
val0             1782 drivers/thunderbolt/icm.c 	ret = pcie2cio_read(icm, TB_CFG_PORT, port0, PHY_PORT_CS1, &val0);
val0             1789 drivers/thunderbolt/icm.c 	val0 &= ~PHY_PORT_CS1_LINK_DISABLE;
val0             1790 drivers/thunderbolt/icm.c 	ret = pcie2cio_write(icm, TB_CFG_PORT, port0, PHY_PORT_CS1, val0);
val0              265 include/linux/hid-sensor-hub.h 			    int *val0, int *val1);
val0               98 sound/i2c/other/pt2258.c 	int val0, val1;
val0              100 sound/i2c/other/pt2258.c 	val0 = 79 - ucontrol->value.integer.value[0];
val0              102 sound/i2c/other/pt2258.c 	if (val0 < 0 || val0 > 79 || val1 < 0 || val1 > 79)
val0              104 sound/i2c/other/pt2258.c 	if (val0 == pt->volume[base] && val1 == pt->volume[base + 1])
val0              107 sound/i2c/other/pt2258.c 	pt->volume[base] = val0;
val0              108 sound/i2c/other/pt2258.c 	bytes[0] = pt2258_channel_code[2 * base] | (val0 / 10);
val0              109 sound/i2c/other/pt2258.c 	bytes[1] = pt2258_channel_code[2 * base + 1] | (val0 % 10);
val0              560 sound/ppc/awacs.c 	int val0, val6;
val0              564 sound/ppc/awacs.c 	val0 = chip->awacs_reg[0] & ~MASK_GAINLINE;
val0              567 sound/ppc/awacs.c 		val0 |= MASK_GAINLINE;
val0              570 sound/ppc/awacs.c 	if (val0 != chip->awacs_reg[0]) {
val0              571 sound/ppc/awacs.c 		snd_pmac_awacs_write_reg(chip, 0, val0);
val0              398 sound/soc/sh/rcar/src.c 	u32 val0, val1;
val0              402 sound/soc/sh/rcar/src.c 	val0 = val1 = OUF_SRC(rsnd_mod_id(mod));
val0              410 sound/soc/sh/rcar/src.c 		val0 = val0 & 0xffff;
val0              414 sound/soc/sh/rcar/src.c 	if ((status0 & val0) || (status1 & val1)) {