v_table 368 drivers/gpu/drm/radeon/radeon_legacy_tv.c uint16_t v_table; v_table 372 drivers/gpu/drm/radeon/radeon_legacy_tv.c v_table = ((tv_uv_adr & RADEON_MAX_UV_ADR_MASK) >> RADEON_MAX_UV_ADR_SHIFT) * 2 + 1; v_table 375 drivers/gpu/drm/radeon/radeon_legacy_tv.c v_table = ((tv_uv_adr & RADEON_TABLE1_BOT_ADR_MASK) >> RADEON_TABLE1_BOT_ADR_SHIFT) * 2 + 1; v_table 378 drivers/gpu/drm/radeon/radeon_legacy_tv.c v_table = ((tv_uv_adr & RADEON_TABLE3_TOP_ADR_MASK) >> RADEON_TABLE3_TOP_ADR_SHIFT) * 2 + 1; v_table 381 drivers/gpu/drm/radeon/radeon_legacy_tv.c v_table = 0; v_table 384 drivers/gpu/drm/radeon/radeon_legacy_tv.c return v_table; v_table 392 drivers/gpu/drm/radeon/radeon_legacy_tv.c uint16_t h_table, v_table; v_table 398 drivers/gpu/drm/radeon/radeon_legacy_tv.c v_table = radeon_get_vtiming_tables_addr(tv_dac->tv.tv_uv_adr); v_table 406 drivers/gpu/drm/radeon/radeon_legacy_tv.c for (i = 0; i < MAX_V_CODE_TIMING_LEN; i += 2, v_table++) { v_table 408 drivers/gpu/drm/radeon/radeon_legacy_tv.c radeon_legacy_tv_write_fifo(radeon_encoder, v_table, tmp); v_table 129 drivers/regulator/hi6421-regulator.c #define HI6421_LDO(_id, _match, v_table, vreg, vmask, ereg, emask, \ v_table 140 drivers/regulator/hi6421-regulator.c .n_voltages = ARRAY_SIZE(v_table), \ v_table 141 drivers/regulator/hi6421-regulator.c .volt_table = v_table, \ v_table 282 drivers/regulator/hi6421-regulator.c #define HI6421_BUCK345(_id, _match, v_table, vreg, vmask, ereg, emask, \ v_table 293 drivers/regulator/hi6421-regulator.c .n_voltages = ARRAY_SIZE(v_table), \ v_table 294 drivers/regulator/hi6421-regulator.c .volt_table = v_table, \ v_table 73 drivers/regulator/hi6421v530-regulator.c #define HI6421V530_LDO(_ID, v_table, vreg, vmask, ereg, emask, \ v_table 83 drivers/regulator/hi6421v530-regulator.c .n_voltages = ARRAY_SIZE(v_table), \ v_table 84 drivers/regulator/hi6421v530-regulator.c .volt_table = v_table, \