v_offset 274 drivers/dma/ipu/ipu_idmac.c u32 u_offset, u32 v_offset) v_offset 278 drivers/dma/ipu/ipu_idmac.c params->pp.vbo_l = v_offset & 0x1ffff; v_offset 279 drivers/dma/ipu/ipu_idmac.c params->pp.vbo_h = v_offset >> 17; v_offset 287 drivers/dma/ipu/ipu_idmac.c u32 v_offset; v_offset 392 drivers/dma/ipu/ipu_idmac.c v_offset = u_offset + u_offset / 4; v_offset 393 drivers/dma/ipu/ipu_idmac.c ipu_ch_param_set_plane_offset(params, u_offset, v_offset); v_offset 400 drivers/dma/ipu/ipu_idmac.c v_offset = stride * height; v_offset 401 drivers/dma/ipu/ipu_idmac.c u_offset = v_offset + v_offset / 2; v_offset 402 drivers/dma/ipu/ipu_idmac.c ipu_ch_param_set_plane_offset(params, u_offset, v_offset); v_offset 410 drivers/dma/ipu/ipu_idmac.c v_offset = u_offset + u_offset / 2; v_offset 411 drivers/dma/ipu/ipu_idmac.c ipu_ch_param_set_plane_offset(params, u_offset, v_offset); v_offset 430 drivers/gpu/drm/radeon/radeon_legacy_tv.c int v_offset, h_offset; v_offset 486 drivers/gpu/drm/radeon/radeon_legacy_tv.c v_offset = ((int)(v_total * h_total) * 2 * tv_dac->v_pos) / (int)(NTSC_TV_LINES_PER_FRAME); v_offset 488 drivers/gpu/drm/radeon/radeon_legacy_tv.c v_offset = ((int)(v_total * h_total) * 2 * tv_dac->v_pos) / (int)(PAL_TV_LINES_PER_FRAME); v_offset 490 drivers/gpu/drm/radeon/radeon_legacy_tv.c restart -= v_offset + h_offset; v_offset 342 drivers/gpu/drm/tegra/dc.c unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp; v_offset 367 drivers/gpu/drm/tegra/dc.c v_offset = window->src.y; v_offset 408 drivers/gpu/drm/tegra/dc.c v_offset += window->src.h - 1; v_offset 411 drivers/gpu/drm/tegra/dc.c tegra_plane_writel(plane, v_offset, DC_WINBUF_ADDR_V_OFFSET); v_offset 474 drivers/gpu/ipu-v3/ipu-cpmem.c unsigned int u_offset, unsigned int v_offset) v_offset 476 drivers/gpu/ipu-v3/ipu-cpmem.c WARN_ON_ONCE((u_offset & 0x7) || (v_offset & 0x7)); v_offset 480 drivers/gpu/ipu-v3/ipu-cpmem.c ipu_ch_param_write_field(ch, IPU_FIELD_VBO, v_offset / 8); v_offset 767 drivers/gpu/ipu-v3/ipu-cpmem.c int offset, u_offset, v_offset; v_offset 785 drivers/gpu/ipu-v3/ipu-cpmem.c v_offset = image->v_offset ? v_offset 786 drivers/gpu/ipu-v3/ipu-cpmem.c image->v_offset : V_OFFSET(pix, image->rect.left, v_offset 790 drivers/gpu/ipu-v3/ipu-cpmem.c u_offset, v_offset); v_offset 797 drivers/gpu/ipu-v3/ipu-cpmem.c v_offset = image->v_offset ? v_offset 798 drivers/gpu/ipu-v3/ipu-cpmem.c image->v_offset : U_OFFSET(pix, image->rect.left, v_offset 802 drivers/gpu/ipu-v3/ipu-cpmem.c u_offset, v_offset); v_offset 809 drivers/gpu/ipu-v3/ipu-cpmem.c v_offset = image->v_offset ? v_offset 810 drivers/gpu/ipu-v3/ipu-cpmem.c image->v_offset : V2_OFFSET(pix, image->rect.left, v_offset 814 drivers/gpu/ipu-v3/ipu-cpmem.c u_offset, v_offset); v_offset 821 drivers/gpu/ipu-v3/ipu-cpmem.c v_offset = image->v_offset ? image->v_offset : 0; v_offset 824 drivers/gpu/ipu-v3/ipu-cpmem.c u_offset, v_offset); v_offset 831 drivers/gpu/ipu-v3/ipu-cpmem.c v_offset = image->v_offset ? image->v_offset : 0; v_offset 834 drivers/gpu/ipu-v3/ipu-cpmem.c u_offset, v_offset); v_offset 1328 drivers/gpu/ipu-v3/ipu-image-convert.c tile_image.v_offset = image->tile[tile_idx[0]].v_off; v_offset 26 drivers/media/common/saa7146/saa7146_hlp.c hyo = vv->standard->v_offset; v_offset 130 drivers/media/pci/saa7146/hexium_gemini.c .v_offset = 28, .v_field = 288, v_offset 135 drivers/media/pci/saa7146/hexium_gemini.c .v_offset = 28, .v_field = 240, v_offset 140 drivers/media/pci/saa7146/hexium_gemini.c .v_offset = 28, .v_field = 288, v_offset 180 drivers/media/pci/saa7146/hexium_orion.c .v_offset = 16, .v_field = 288, v_offset 185 drivers/media/pci/saa7146/hexium_orion.c .v_offset = 16, .v_field = 240, v_offset 190 drivers/media/pci/saa7146/hexium_orion.c .v_offset = 16, .v_field = 288, v_offset 785 drivers/media/pci/saa7146/mxb.c .v_offset = 0x17, .v_field = 288, v_offset 790 drivers/media/pci/saa7146/mxb.c .v_offset = 0x17, .v_field = 288, v_offset 795 drivers/media/pci/saa7146/mxb.c .v_offset = 0x16, .v_field = 240, v_offset 800 drivers/media/pci/saa7146/mxb.c .v_offset = 0x14, .v_field = 288, v_offset 865 drivers/media/pci/ttpci/av7110_v4l.c .v_offset = 0x15, .v_field = 288, v_offset 870 drivers/media/pci/ttpci/av7110_v4l.c .v_offset = 0x10, .v_field = 244, v_offset 879 drivers/media/pci/ttpci/av7110_v4l.c .v_offset = 0x1b, .v_field = 288, v_offset 884 drivers/media/pci/ttpci/av7110_v4l.c .v_offset = 0x10, .v_field = 244, v_offset 893 drivers/media/pci/ttpci/av7110_v4l.c .v_offset = 0x14, .v_field = 288, v_offset 898 drivers/media/pci/ttpci/av7110_v4l.c .v_offset = 0x10, .v_field = 244, v_offset 1511 drivers/media/pci/ttpci/budget-av.c .v_offset = 0x17,.v_field = 288, v_offset 1516 drivers/media/pci/ttpci/budget-av.c .v_offset = 0x16,.v_field = 240, v_offset 365 fs/hugetlbfs/inode.c unsigned long v_offset; v_offset 375 fs/hugetlbfs/inode.c v_offset = (start - vma->vm_pgoff) << PAGE_SHIFT; v_offset 377 fs/hugetlbfs/inode.c v_offset = 0; v_offset 388 fs/hugetlbfs/inode.c unmap_hugepage_range(vma, vma->vm_start + v_offset, v_end, v_offset 47 include/media/drv-intf/saa7146_vv.h int v_offset; /* number of lines of vertical offset before processing */ v_offset 251 include/video/imx-ipu-v3.h u32 v_offset; v_offset 276 include/video/imx-ipu-v3.h unsigned int v_offset);