v_blank_dram_speed_change_margin  533 drivers/gpu/drm/amd/display/dc/calcs/calcs_logger.h 					i, bw_fixed_to_int(data->v_blank_dram_speed_change_margin[i]));
v_blank_dram_speed_change_margin 1430 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 				data->v_blank_dram_speed_change_margin[k] = bw_sub(bw_sub(bw_sub(bw_div(bw_mul((bw_sub(data->v_total[k], bw_sub(bw_div(data->src_height[k], data->v_scale_ratio[k]), bw_int_to_fixed(4)))), data->h_total[k]), data->pixel_rate[k]), vbios->nbp_state_change_latency), data->dmif_burst_time[low][s_low]), data->dram_speed_change_line_source_transfer_time[k][low][s_low]);
v_blank_dram_speed_change_margin 1431 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 				data->min_vblank_dram_speed_change_margin = bw_min2(data->min_vblank_dram_speed_change_margin, data->v_blank_dram_speed_change_margin[k]);
v_blank_dram_speed_change_margin 1434 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 				data->v_blank_dram_speed_change_margin[k] = bw_sub(bw_sub(bw_sub(bw_sub(bw_div(bw_mul((bw_sub(data->v_total[k], bw_sub(bw_div(data->src_height[k], data->v_scale_ratio[k]), bw_int_to_fixed(4)))), data->h_total[k]), data->pixel_rate[k]), vbios->nbp_state_change_latency), data->dmif_burst_time[low][s_low]), data->mcifwr_burst_time[low][s_low]), data->dram_speed_change_line_source_transfer_time[k][low][s_low]);
v_blank_dram_speed_change_margin 1435 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 				data->min_vblank_dram_speed_change_margin = bw_min2(data->min_vblank_dram_speed_change_margin, data->v_blank_dram_speed_change_margin[k]);
v_blank_dram_speed_change_margin 1441 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 		if (data->enable[i] == 1 && data->display_pstate_change_enable[i] == 0 && bw_mtn(data->v_blank_dram_speed_change_margin[i], bw_int_to_fixed(0))) {
v_blank_dram_speed_change_margin  451 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h 	struct bw_fixed v_blank_dram_speed_change_margin[maximum_number_of_surfaces];