vCG_SPLL_FUNC_CNTL_3 2971 drivers/gpu/drm/amd/amdgpu/si_dpm.c 		fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT;
vCG_SPLL_FUNC_CNTL_3 4867 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
vCG_SPLL_FUNC_CNTL_3 5065 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
vCG_SPLL_FUNC_CNTL_3 5306 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3;
vCG_SPLL_FUNC_CNTL_3 5326 drivers/gpu/drm/amd/amdgpu/si_dpm.c 		sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3);
vCG_SPLL_FUNC_CNTL_3  369 drivers/gpu/drm/amd/amdgpu/si_dpm.h     uint32_t        vCG_SPLL_FUNC_CNTL_3;
vCG_SPLL_FUNC_CNTL_3  711 drivers/gpu/drm/amd/amdgpu/si_dpm.h     uint32_t        vCG_SPLL_FUNC_CNTL_3;
vCG_SPLL_FUNC_CNTL_3  107 drivers/gpu/drm/amd/amdgpu/sislands_smc.h     uint32_t    vCG_SPLL_FUNC_CNTL_3;
vCG_SPLL_FUNC_CNTL_3 4282 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	data->clock_registers.vCG_SPLL_FUNC_CNTL_3       =
vCG_SPLL_FUNC_CNTL_3  115 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h 	uint32_t  vCG_SPLL_FUNC_CNTL_3;
vCG_SPLL_FUNC_CNTL_3  301 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	uint32_t spll_func_cntl_3          = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
vCG_SPLL_FUNC_CNTL_3 1422 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	table->ACPILevel.CgSpllFuncCntl3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
vCG_SPLL_FUNC_CNTL_3  863 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	uint32_t spll_func_cntl_3          = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
vCG_SPLL_FUNC_CNTL_3 1356 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	table->ACPILevel.CgSpllFuncCntl3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
vCG_SPLL_FUNC_CNTL_3  801 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	uint32_t spll_func_cntl_3          = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
vCG_SPLL_FUNC_CNTL_3 1470 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	table->ACPILevel.CgSpllFuncCntl3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
vCG_SPLL_FUNC_CNTL_3  544 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	uint32_t spll_func_cntl_3          = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
vCG_SPLL_FUNC_CNTL_3 1219 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	table->ACPILevel.CgSpllFuncCntl3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
vCG_SPLL_FUNC_CNTL_3 1269 drivers/gpu/drm/radeon/cypress_dpm.c 	table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
vCG_SPLL_FUNC_CNTL_3 1452 drivers/gpu/drm/radeon/cypress_dpm.c 	table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
vCG_SPLL_FUNC_CNTL_3 1715 drivers/gpu/drm/radeon/ni_dpm.c 	table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
vCG_SPLL_FUNC_CNTL_3 1916 drivers/gpu/drm/radeon/ni_dpm.c 	table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3);
vCG_SPLL_FUNC_CNTL_3 2061 drivers/gpu/drm/radeon/ni_dpm.c 	sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3;
vCG_SPLL_FUNC_CNTL_3 2081 drivers/gpu/drm/radeon/ni_dpm.c 		sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3);
vCG_SPLL_FUNC_CNTL_3 2117 drivers/gpu/drm/radeon/ni_dpm.c 		fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT;
vCG_SPLL_FUNC_CNTL_3   60 drivers/gpu/drm/radeon/nislands_smc.h     uint32_t        vCG_SPLL_FUNC_CNTL_3;
vCG_SPLL_FUNC_CNTL_3  111 drivers/gpu/drm/radeon/rv730_dpm.c 	sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3);
vCG_SPLL_FUNC_CNTL_3  306 drivers/gpu/drm/radeon/rv730_dpm.c 	table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3);
vCG_SPLL_FUNC_CNTL_3  348 drivers/gpu/drm/radeon/rv730_dpm.c 	table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
vCG_SPLL_FUNC_CNTL_3  179 drivers/gpu/drm/radeon/rv740_dpm.c 	sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3);
vCG_SPLL_FUNC_CNTL_3  384 drivers/gpu/drm/radeon/rv740_dpm.c 	table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3);
vCG_SPLL_FUNC_CNTL_3  558 drivers/gpu/drm/radeon/rv770_dpm.c 	sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3);
vCG_SPLL_FUNC_CNTL_3  993 drivers/gpu/drm/radeon/rv770_dpm.c 	table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3);
vCG_SPLL_FUNC_CNTL_3 1055 drivers/gpu/drm/radeon/rv770_dpm.c 	table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
vCG_SPLL_FUNC_CNTL_3   38 drivers/gpu/drm/radeon/rv770_smc.h     uint32_t        vCG_SPLL_FUNC_CNTL_3;
vCG_SPLL_FUNC_CNTL_3 2873 drivers/gpu/drm/radeon/si_dpm.c 		fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT;
vCG_SPLL_FUNC_CNTL_3 4403 drivers/gpu/drm/radeon/si_dpm.c 	table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
vCG_SPLL_FUNC_CNTL_3 4602 drivers/gpu/drm/radeon/si_dpm.c 	table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
vCG_SPLL_FUNC_CNTL_3 4844 drivers/gpu/drm/radeon/si_dpm.c 	sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3;
vCG_SPLL_FUNC_CNTL_3 4864 drivers/gpu/drm/radeon/si_dpm.c 		sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3);
vCG_SPLL_FUNC_CNTL_3  107 drivers/gpu/drm/radeon/sislands_smc.h     uint32_t    vCG_SPLL_FUNC_CNTL_3;