vCG_SPLL_FUNC_CNTL 2970 drivers/gpu/drm/amd/amdgpu/si_dpm.c 		p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & SPLL_PDIV_A_MASK) >> SPLL_PDIV_A_SHIFT;
vCG_SPLL_FUNC_CNTL 4863 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
vCG_SPLL_FUNC_CNTL 5061 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
vCG_SPLL_FUNC_CNTL 5304 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl;
vCG_SPLL_FUNC_CNTL 5324 drivers/gpu/drm/amd/amdgpu/si_dpm.c 		sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL);
vCG_SPLL_FUNC_CNTL  367 drivers/gpu/drm/amd/amdgpu/si_dpm.h     uint32_t        vCG_SPLL_FUNC_CNTL;
vCG_SPLL_FUNC_CNTL  709 drivers/gpu/drm/amd/amdgpu/si_dpm.h     uint32_t        vCG_SPLL_FUNC_CNTL;
vCG_SPLL_FUNC_CNTL  105 drivers/gpu/drm/amd/amdgpu/sislands_smc.h     uint32_t    vCG_SPLL_FUNC_CNTL;
vCG_SPLL_FUNC_CNTL 4278 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	data->clock_registers.vCG_SPLL_FUNC_CNTL         =
vCG_SPLL_FUNC_CNTL  113 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h 	uint32_t  vCG_SPLL_FUNC_CNTL;
vCG_SPLL_FUNC_CNTL  300 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	uint32_t spll_func_cntl            = data->clock_registers.vCG_SPLL_FUNC_CNTL;
vCG_SPLL_FUNC_CNTL 1383 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	uint32_t spll_func_cntl    = data->clock_registers.vCG_SPLL_FUNC_CNTL;
vCG_SPLL_FUNC_CNTL  862 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	uint32_t spll_func_cntl            = data->clock_registers.vCG_SPLL_FUNC_CNTL;
vCG_SPLL_FUNC_CNTL 1311 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	uint32_t spll_func_cntl    = data->clock_registers.vCG_SPLL_FUNC_CNTL;
vCG_SPLL_FUNC_CNTL  800 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	uint32_t spll_func_cntl            = data->clock_registers.vCG_SPLL_FUNC_CNTL;
vCG_SPLL_FUNC_CNTL 1431 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	uint32_t spll_func_cntl    = data->clock_registers.vCG_SPLL_FUNC_CNTL;
vCG_SPLL_FUNC_CNTL  543 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	uint32_t spll_func_cntl            = data->clock_registers.vCG_SPLL_FUNC_CNTL;
vCG_SPLL_FUNC_CNTL 1183 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	uint32_t spll_func_cntl    = data->clock_registers.vCG_SPLL_FUNC_CNTL;
vCG_SPLL_FUNC_CNTL 1265 drivers/gpu/drm/radeon/cypress_dpm.c 	table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
vCG_SPLL_FUNC_CNTL 1448 drivers/gpu/drm/radeon/cypress_dpm.c 	table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
vCG_SPLL_FUNC_CNTL 1711 drivers/gpu/drm/radeon/ni_dpm.c 	table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
vCG_SPLL_FUNC_CNTL 1914 drivers/gpu/drm/radeon/ni_dpm.c 	table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl);
vCG_SPLL_FUNC_CNTL 2059 drivers/gpu/drm/radeon/ni_dpm.c 	sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl;
vCG_SPLL_FUNC_CNTL 2079 drivers/gpu/drm/radeon/ni_dpm.c 		sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL);
vCG_SPLL_FUNC_CNTL 2116 drivers/gpu/drm/radeon/ni_dpm.c 		p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & SPLL_PDIV_A_MASK) >> SPLL_PDIV_A_SHIFT;
vCG_SPLL_FUNC_CNTL   58 drivers/gpu/drm/radeon/nislands_smc.h     uint32_t        vCG_SPLL_FUNC_CNTL;
vCG_SPLL_FUNC_CNTL  109 drivers/gpu/drm/radeon/rv730_dpm.c 	sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl);
vCG_SPLL_FUNC_CNTL  304 drivers/gpu/drm/radeon/rv730_dpm.c 	table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl);
vCG_SPLL_FUNC_CNTL  344 drivers/gpu/drm/radeon/rv730_dpm.c 	table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
vCG_SPLL_FUNC_CNTL  177 drivers/gpu/drm/radeon/rv740_dpm.c 	sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl);
vCG_SPLL_FUNC_CNTL  382 drivers/gpu/drm/radeon/rv740_dpm.c 	table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl);
vCG_SPLL_FUNC_CNTL  556 drivers/gpu/drm/radeon/rv770_dpm.c 	sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl);
vCG_SPLL_FUNC_CNTL  991 drivers/gpu/drm/radeon/rv770_dpm.c 	table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl);
vCG_SPLL_FUNC_CNTL 1051 drivers/gpu/drm/radeon/rv770_dpm.c 	table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
vCG_SPLL_FUNC_CNTL   36 drivers/gpu/drm/radeon/rv770_smc.h     uint32_t        vCG_SPLL_FUNC_CNTL;
vCG_SPLL_FUNC_CNTL 2872 drivers/gpu/drm/radeon/si_dpm.c 		p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & SPLL_PDIV_A_MASK) >> SPLL_PDIV_A_SHIFT;
vCG_SPLL_FUNC_CNTL 4399 drivers/gpu/drm/radeon/si_dpm.c 	table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
vCG_SPLL_FUNC_CNTL 4598 drivers/gpu/drm/radeon/si_dpm.c 	table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
vCG_SPLL_FUNC_CNTL 4842 drivers/gpu/drm/radeon/si_dpm.c 	sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl;
vCG_SPLL_FUNC_CNTL 4862 drivers/gpu/drm/radeon/si_dpm.c 		sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL);
vCG_SPLL_FUNC_CNTL  105 drivers/gpu/drm/radeon/sislands_smc.h     uint32_t    vCG_SPLL_FUNC_CNTL;