v3d 33 drivers/gpu/drm/v3d/v3d_bo.c struct v3d_dev *v3d = to_v3d_dev(obj->dev); v3d 38 drivers/gpu/drm/v3d/v3d_bo.c mutex_lock(&v3d->bo_lock); v3d 39 drivers/gpu/drm/v3d/v3d_bo.c v3d->bo_stats.num_allocated--; v3d 40 drivers/gpu/drm/v3d/v3d_bo.c v3d->bo_stats.pages_allocated -= obj->size >> PAGE_SHIFT; v3d 41 drivers/gpu/drm/v3d/v3d_bo.c mutex_unlock(&v3d->bo_lock); v3d 43 drivers/gpu/drm/v3d/v3d_bo.c spin_lock(&v3d->mm_lock); v3d 45 drivers/gpu/drm/v3d/v3d_bo.c spin_unlock(&v3d->mm_lock); v3d 90 drivers/gpu/drm/v3d/v3d_bo.c struct v3d_dev *v3d = to_v3d_dev(obj->dev); v3d 102 drivers/gpu/drm/v3d/v3d_bo.c spin_lock(&v3d->mm_lock); v3d 107 drivers/gpu/drm/v3d/v3d_bo.c ret = drm_mm_insert_node_generic(&v3d->mm, &bo->node, v3d 110 drivers/gpu/drm/v3d/v3d_bo.c spin_unlock(&v3d->mm_lock); v3d 115 drivers/gpu/drm/v3d/v3d_bo.c mutex_lock(&v3d->bo_lock); v3d 116 drivers/gpu/drm/v3d/v3d_bo.c v3d->bo_stats.num_allocated++; v3d 117 drivers/gpu/drm/v3d/v3d_bo.c v3d->bo_stats.pages_allocated += obj->size >> PAGE_SHIFT; v3d 118 drivers/gpu/drm/v3d/v3d_bo.c mutex_unlock(&v3d->bo_lock); v3d 84 drivers/gpu/drm/v3d/v3d_debugfs.c struct v3d_dev *v3d = to_v3d_dev(dev); v3d 93 drivers/gpu/drm/v3d/v3d_debugfs.c if (v3d->ver < 41) { v3d 102 drivers/gpu/drm/v3d/v3d_debugfs.c for (core = 0; core < v3d->cores; core++) { v3d 112 drivers/gpu/drm/v3d/v3d_debugfs.c if (v3d_has_csd(v3d)) { v3d 131 drivers/gpu/drm/v3d/v3d_debugfs.c struct v3d_dev *v3d = to_v3d_dev(dev); v3d 135 drivers/gpu/drm/v3d/v3d_debugfs.c ret = pm_runtime_get_sync(v3d->dev); v3d 190 drivers/gpu/drm/v3d/v3d_debugfs.c pm_runtime_mark_last_busy(v3d->dev); v3d 191 drivers/gpu/drm/v3d/v3d_debugfs.c pm_runtime_put_autosuspend(v3d->dev); v3d 200 drivers/gpu/drm/v3d/v3d_debugfs.c struct v3d_dev *v3d = to_v3d_dev(dev); v3d 202 drivers/gpu/drm/v3d/v3d_debugfs.c mutex_lock(&v3d->bo_lock); v3d 204 drivers/gpu/drm/v3d/v3d_debugfs.c v3d->bo_stats.num_allocated); v3d 206 drivers/gpu/drm/v3d/v3d_debugfs.c (long)v3d->bo_stats.pages_allocated << (PAGE_SHIFT - 10)); v3d 207 drivers/gpu/drm/v3d/v3d_debugfs.c mutex_unlock(&v3d->bo_lock); v3d 216 drivers/gpu/drm/v3d/v3d_debugfs.c struct v3d_dev *v3d = to_v3d_dev(dev); v3d 222 drivers/gpu/drm/v3d/v3d_debugfs.c ret = pm_runtime_get_sync(v3d->dev); v3d 226 drivers/gpu/drm/v3d/v3d_debugfs.c if (v3d->ver >= 40) { v3d 248 drivers/gpu/drm/v3d/v3d_debugfs.c pm_runtime_mark_last_busy(v3d->dev); v3d 249 drivers/gpu/drm/v3d/v3d_debugfs.c pm_runtime_put_autosuspend(v3d->dev); v3d 44 drivers/gpu/drm/v3d/v3d_drv.c struct v3d_dev *v3d = to_v3d_dev(drm); v3d 46 drivers/gpu/drm/v3d/v3d_drv.c v3d_irq_disable(v3d); v3d 48 drivers/gpu/drm/v3d/v3d_drv.c clk_disable_unprepare(v3d->clk); v3d 56 drivers/gpu/drm/v3d/v3d_drv.c struct v3d_dev *v3d = to_v3d_dev(drm); v3d 59 drivers/gpu/drm/v3d/v3d_drv.c ret = clk_prepare_enable(v3d->clk); v3d 65 drivers/gpu/drm/v3d/v3d_drv.c v3d_mmu_set_page_table(v3d); v3d 66 drivers/gpu/drm/v3d/v3d_drv.c v3d_irq_enable(v3d); v3d 79 drivers/gpu/drm/v3d/v3d_drv.c struct v3d_dev *v3d = to_v3d_dev(dev); v3d 107 drivers/gpu/drm/v3d/v3d_drv.c ret = pm_runtime_get_sync(v3d->dev); v3d 116 drivers/gpu/drm/v3d/v3d_drv.c pm_runtime_mark_last_busy(v3d->dev); v3d 117 drivers/gpu/drm/v3d/v3d_drv.c pm_runtime_put_autosuspend(v3d->dev); v3d 127 drivers/gpu/drm/v3d/v3d_drv.c args->value = v3d_has_csd(v3d); v3d 138 drivers/gpu/drm/v3d/v3d_drv.c struct v3d_dev *v3d = to_v3d_dev(dev); v3d 147 drivers/gpu/drm/v3d/v3d_drv.c v3d_priv->v3d = v3d; v3d 150 drivers/gpu/drm/v3d/v3d_drv.c rq = &v3d->queue[i].sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL]; v3d 229 drivers/gpu/drm/v3d/v3d_drv.c map_regs(struct v3d_dev *v3d, void __iomem **regs, const char *name) v3d 232 drivers/gpu/drm/v3d/v3d_drv.c platform_get_resource_byname(v3d->pdev, IORESOURCE_MEM, name); v3d 234 drivers/gpu/drm/v3d/v3d_drv.c *regs = devm_ioremap_resource(v3d->dev, res); v3d 242 drivers/gpu/drm/v3d/v3d_drv.c struct v3d_dev *v3d; v3d 248 drivers/gpu/drm/v3d/v3d_drv.c v3d = kzalloc(sizeof(*v3d), GFP_KERNEL); v3d 249 drivers/gpu/drm/v3d/v3d_drv.c if (!v3d) v3d 251 drivers/gpu/drm/v3d/v3d_drv.c v3d->dev = dev; v3d 252 drivers/gpu/drm/v3d/v3d_drv.c v3d->pdev = pdev; v3d 253 drivers/gpu/drm/v3d/v3d_drv.c drm = &v3d->drm; v3d 255 drivers/gpu/drm/v3d/v3d_drv.c ret = map_regs(v3d, &v3d->hub_regs, "hub"); v3d 259 drivers/gpu/drm/v3d/v3d_drv.c ret = map_regs(v3d, &v3d->core_regs[0], "core0"); v3d 266 drivers/gpu/drm/v3d/v3d_drv.c v3d->va_width = 30 + V3D_GET_FIELD(mmu_debug, V3D_MMU_VA_WIDTH); v3d 269 drivers/gpu/drm/v3d/v3d_drv.c v3d->ver = (V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_TVER) * 10 + v3d 271 drivers/gpu/drm/v3d/v3d_drv.c v3d->cores = V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_NCORES); v3d 272 drivers/gpu/drm/v3d/v3d_drv.c WARN_ON(v3d->cores > 1); /* multicore not yet implemented */ v3d 274 drivers/gpu/drm/v3d/v3d_drv.c v3d->reset = devm_reset_control_get_exclusive(dev, NULL); v3d 275 drivers/gpu/drm/v3d/v3d_drv.c if (IS_ERR(v3d->reset)) { v3d 276 drivers/gpu/drm/v3d/v3d_drv.c ret = PTR_ERR(v3d->reset); v3d 281 drivers/gpu/drm/v3d/v3d_drv.c v3d->reset = NULL; v3d 282 drivers/gpu/drm/v3d/v3d_drv.c ret = map_regs(v3d, &v3d->bridge_regs, "bridge"); v3d 290 drivers/gpu/drm/v3d/v3d_drv.c if (v3d->ver < 41) { v3d 291 drivers/gpu/drm/v3d/v3d_drv.c ret = map_regs(v3d, &v3d->gca_regs, "gca"); v3d 296 drivers/gpu/drm/v3d/v3d_drv.c v3d->mmu_scratch = dma_alloc_wc(dev, 4096, &v3d->mmu_scratch_paddr, v3d 298 drivers/gpu/drm/v3d/v3d_drv.c if (!v3d->mmu_scratch) { v3d 308 drivers/gpu/drm/v3d/v3d_drv.c ret = drm_dev_init(&v3d->drm, &v3d_drm_driver, dev); v3d 313 drivers/gpu/drm/v3d/v3d_drv.c drm->dev_private = v3d; v3d 319 drivers/gpu/drm/v3d/v3d_drv.c ret = v3d_irq_init(v3d); v3d 330 drivers/gpu/drm/v3d/v3d_drv.c v3d_irq_disable(v3d); v3d 336 drivers/gpu/drm/v3d/v3d_drv.c dma_free_wc(dev, 4096, v3d->mmu_scratch, v3d->mmu_scratch_paddr); v3d 338 drivers/gpu/drm/v3d/v3d_drv.c kfree(v3d); v3d 345 drivers/gpu/drm/v3d/v3d_drv.c struct v3d_dev *v3d = to_v3d_dev(drm); v3d 353 drivers/gpu/drm/v3d/v3d_drv.c dma_free_wc(v3d->dev, 4096, v3d->mmu_scratch, v3d->mmu_scratch_paddr); v3d 128 drivers/gpu/drm/v3d/v3d_drv.h v3d_has_csd(struct v3d_dev *v3d) v3d 130 drivers/gpu/drm/v3d/v3d_drv.h return v3d->ver >= 41; v3d 135 drivers/gpu/drm/v3d/v3d_drv.h struct v3d_dev *v3d; v3d 171 drivers/gpu/drm/v3d/v3d_drv.h #define V3D_READ(offset) readl(v3d->hub_regs + offset) v3d 172 drivers/gpu/drm/v3d/v3d_drv.h #define V3D_WRITE(offset, val) writel(val, v3d->hub_regs + offset) v3d 174 drivers/gpu/drm/v3d/v3d_drv.h #define V3D_BRIDGE_READ(offset) readl(v3d->bridge_regs + offset) v3d 175 drivers/gpu/drm/v3d/v3d_drv.h #define V3D_BRIDGE_WRITE(offset, val) writel(val, v3d->bridge_regs + offset) v3d 177 drivers/gpu/drm/v3d/v3d_drv.h #define V3D_GCA_READ(offset) readl(v3d->gca_regs + offset) v3d 178 drivers/gpu/drm/v3d/v3d_drv.h #define V3D_GCA_WRITE(offset, val) writel(val, v3d->gca_regs + offset) v3d 180 drivers/gpu/drm/v3d/v3d_drv.h #define V3D_CORE_READ(core, offset) readl(v3d->core_regs[core] + offset) v3d 181 drivers/gpu/drm/v3d/v3d_drv.h #define V3D_CORE_WRITE(core, offset, val) writel(val, v3d->core_regs[core] + offset) v3d 188 drivers/gpu/drm/v3d/v3d_drv.h struct v3d_dev *v3d; v3d 308 drivers/gpu/drm/v3d/v3d_drv.h struct dma_fence *v3d_fence_create(struct v3d_dev *v3d, enum v3d_queue queue); v3d 322 drivers/gpu/drm/v3d/v3d_drv.h void v3d_reset(struct v3d_dev *v3d); v3d 323 drivers/gpu/drm/v3d/v3d_drv.h void v3d_invalidate_caches(struct v3d_dev *v3d); v3d 324 drivers/gpu/drm/v3d/v3d_drv.h void v3d_clean_caches(struct v3d_dev *v3d); v3d 327 drivers/gpu/drm/v3d/v3d_drv.h int v3d_irq_init(struct v3d_dev *v3d); v3d 328 drivers/gpu/drm/v3d/v3d_drv.h void v3d_irq_enable(struct v3d_dev *v3d); v3d 329 drivers/gpu/drm/v3d/v3d_drv.h void v3d_irq_disable(struct v3d_dev *v3d); v3d 330 drivers/gpu/drm/v3d/v3d_drv.h void v3d_irq_reset(struct v3d_dev *v3d); v3d 335 drivers/gpu/drm/v3d/v3d_drv.h int v3d_mmu_set_page_table(struct v3d_dev *v3d); v3d 340 drivers/gpu/drm/v3d/v3d_drv.h int v3d_sched_init(struct v3d_dev *v3d); v3d 341 drivers/gpu/drm/v3d/v3d_drv.h void v3d_sched_fini(struct v3d_dev *v3d); v3d 6 drivers/gpu/drm/v3d/v3d_fence.c struct dma_fence *v3d_fence_create(struct v3d_dev *v3d, enum v3d_queue queue) v3d 14 drivers/gpu/drm/v3d/v3d_fence.c fence->dev = &v3d->drm; v3d 16 drivers/gpu/drm/v3d/v3d_fence.c fence->seqno = ++v3d->queue[queue].emit_seqno; v3d 17 drivers/gpu/drm/v3d/v3d_fence.c dma_fence_init(&fence->base, &v3d_fence_ops, &v3d->job_lock, v3d 18 drivers/gpu/drm/v3d/v3d_fence.c v3d->queue[queue].fence_context, fence->seqno); v3d 22 drivers/gpu/drm/v3d/v3d_gem.c v3d_init_core(struct v3d_dev *v3d, int core) v3d 30 drivers/gpu/drm/v3d/v3d_gem.c if (v3d->ver < 40) v3d 42 drivers/gpu/drm/v3d/v3d_gem.c v3d_init_hw_state(struct v3d_dev *v3d) v3d 44 drivers/gpu/drm/v3d/v3d_gem.c v3d_init_core(v3d, 0); v3d 48 drivers/gpu/drm/v3d/v3d_gem.c v3d_idle_axi(struct v3d_dev *v3d, int core) v3d 61 drivers/gpu/drm/v3d/v3d_gem.c v3d_idle_gca(struct v3d_dev *v3d) v3d 63 drivers/gpu/drm/v3d/v3d_gem.c if (v3d->ver >= 41) v3d 76 drivers/gpu/drm/v3d/v3d_gem.c v3d_reset_by_bridge(struct v3d_dev *v3d) v3d 99 drivers/gpu/drm/v3d/v3d_gem.c v3d_reset_v3d(struct v3d_dev *v3d) v3d 101 drivers/gpu/drm/v3d/v3d_gem.c if (v3d->reset) v3d 102 drivers/gpu/drm/v3d/v3d_gem.c reset_control_reset(v3d->reset); v3d 104 drivers/gpu/drm/v3d/v3d_gem.c v3d_reset_by_bridge(v3d); v3d 106 drivers/gpu/drm/v3d/v3d_gem.c v3d_init_hw_state(v3d); v3d 110 drivers/gpu/drm/v3d/v3d_gem.c v3d_reset(struct v3d_dev *v3d) v3d 112 drivers/gpu/drm/v3d/v3d_gem.c struct drm_device *dev = &v3d->drm; v3d 121 drivers/gpu/drm/v3d/v3d_gem.c v3d_idle_axi(v3d, 0); v3d 123 drivers/gpu/drm/v3d/v3d_gem.c v3d_idle_gca(v3d); v3d 124 drivers/gpu/drm/v3d/v3d_gem.c v3d_reset_v3d(v3d); v3d 126 drivers/gpu/drm/v3d/v3d_gem.c v3d_mmu_set_page_table(v3d); v3d 127 drivers/gpu/drm/v3d/v3d_gem.c v3d_irq_reset(v3d); v3d 133 drivers/gpu/drm/v3d/v3d_gem.c v3d_flush_l3(struct v3d_dev *v3d) v3d 135 drivers/gpu/drm/v3d/v3d_gem.c if (v3d->ver < 41) { v3d 141 drivers/gpu/drm/v3d/v3d_gem.c if (v3d->ver < 33) { v3d 152 drivers/gpu/drm/v3d/v3d_gem.c v3d_invalidate_l2c(struct v3d_dev *v3d, int core) v3d 154 drivers/gpu/drm/v3d/v3d_gem.c if (v3d->ver > 32) v3d 164 drivers/gpu/drm/v3d/v3d_gem.c v3d_flush_l2t(struct v3d_dev *v3d, int core) v3d 173 drivers/gpu/drm/v3d/v3d_gem.c mutex_lock(&v3d->cache_clean_lock); v3d 177 drivers/gpu/drm/v3d/v3d_gem.c mutex_unlock(&v3d->cache_clean_lock); v3d 189 drivers/gpu/drm/v3d/v3d_gem.c v3d_clean_caches(struct v3d_dev *v3d) v3d 191 drivers/gpu/drm/v3d/v3d_gem.c struct drm_device *dev = &v3d->drm; v3d 202 drivers/gpu/drm/v3d/v3d_gem.c mutex_lock(&v3d->cache_clean_lock); v3d 212 drivers/gpu/drm/v3d/v3d_gem.c mutex_unlock(&v3d->cache_clean_lock); v3d 219 drivers/gpu/drm/v3d/v3d_gem.c v3d_invalidate_slices(struct v3d_dev *v3d, int core) v3d 229 drivers/gpu/drm/v3d/v3d_gem.c v3d_invalidate_caches(struct v3d_dev *v3d) v3d 236 drivers/gpu/drm/v3d/v3d_gem.c v3d_flush_l3(v3d); v3d 237 drivers/gpu/drm/v3d/v3d_gem.c v3d_invalidate_l2c(v3d, 0); v3d 238 drivers/gpu/drm/v3d/v3d_gem.c v3d_flush_l2t(v3d, 0); v3d 239 drivers/gpu/drm/v3d/v3d_gem.c v3d_invalidate_slices(v3d, 0); v3d 373 drivers/gpu/drm/v3d/v3d_gem.c pm_runtime_mark_last_busy(job->v3d->dev); v3d 374 drivers/gpu/drm/v3d/v3d_gem.c pm_runtime_put_autosuspend(job->v3d->dev); v3d 432 drivers/gpu/drm/v3d/v3d_gem.c v3d_job_init(struct v3d_dev *v3d, struct drm_file *file_priv, v3d 439 drivers/gpu/drm/v3d/v3d_gem.c job->v3d = v3d; v3d 442 drivers/gpu/drm/v3d/v3d_gem.c ret = pm_runtime_get_sync(v3d->dev); v3d 461 drivers/gpu/drm/v3d/v3d_gem.c pm_runtime_put_autosuspend(v3d->dev); v3d 528 drivers/gpu/drm/v3d/v3d_gem.c struct v3d_dev *v3d = to_v3d_dev(dev); v3d 536 drivers/gpu/drm/v3d/v3d_gem.c trace_v3d_submit_cl_ioctl(&v3d->drm, args->rcl_start, args->rcl_end); v3d 551 drivers/gpu/drm/v3d/v3d_gem.c ret = v3d_job_init(v3d, file_priv, &render->base, v3d 565 drivers/gpu/drm/v3d/v3d_gem.c ret = v3d_job_init(v3d, file_priv, &bin->base, v3d 590 drivers/gpu/drm/v3d/v3d_gem.c mutex_lock(&v3d->sched_lock); v3d 605 drivers/gpu/drm/v3d/v3d_gem.c mutex_unlock(&v3d->sched_lock); v3d 620 drivers/gpu/drm/v3d/v3d_gem.c mutex_unlock(&v3d->sched_lock); v3d 644 drivers/gpu/drm/v3d/v3d_gem.c struct v3d_dev *v3d = to_v3d_dev(dev); v3d 651 drivers/gpu/drm/v3d/v3d_gem.c trace_v3d_submit_tfu_ioctl(&v3d->drm, args->iia); v3d 657 drivers/gpu/drm/v3d/v3d_gem.c ret = v3d_job_init(v3d, file_priv, &job->base, v3d 701 drivers/gpu/drm/v3d/v3d_gem.c mutex_lock(&v3d->sched_lock); v3d 705 drivers/gpu/drm/v3d/v3d_gem.c mutex_unlock(&v3d->sched_lock); v3d 717 drivers/gpu/drm/v3d/v3d_gem.c mutex_unlock(&v3d->sched_lock); v3d 739 drivers/gpu/drm/v3d/v3d_gem.c struct v3d_dev *v3d = to_v3d_dev(dev); v3d 747 drivers/gpu/drm/v3d/v3d_gem.c trace_v3d_submit_csd_ioctl(&v3d->drm, args->cfg[5], args->cfg[6]); v3d 749 drivers/gpu/drm/v3d/v3d_gem.c if (!v3d_has_csd(v3d)) { v3d 758 drivers/gpu/drm/v3d/v3d_gem.c ret = v3d_job_init(v3d, file_priv, &job->base, v3d 772 drivers/gpu/drm/v3d/v3d_gem.c ret = v3d_job_init(v3d, file_priv, clean_job, v3d_job_free, 0); v3d 790 drivers/gpu/drm/v3d/v3d_gem.c mutex_lock(&v3d->sched_lock); v3d 803 drivers/gpu/drm/v3d/v3d_gem.c mutex_unlock(&v3d->sched_lock); v3d 817 drivers/gpu/drm/v3d/v3d_gem.c mutex_unlock(&v3d->sched_lock); v3d 830 drivers/gpu/drm/v3d/v3d_gem.c struct v3d_dev *v3d = to_v3d_dev(dev); v3d 835 drivers/gpu/drm/v3d/v3d_gem.c v3d->queue[i].fence_context = dma_fence_context_alloc(1); v3d 837 drivers/gpu/drm/v3d/v3d_gem.c spin_lock_init(&v3d->mm_lock); v3d 838 drivers/gpu/drm/v3d/v3d_gem.c spin_lock_init(&v3d->job_lock); v3d 839 drivers/gpu/drm/v3d/v3d_gem.c mutex_init(&v3d->bo_lock); v3d 840 drivers/gpu/drm/v3d/v3d_gem.c mutex_init(&v3d->reset_lock); v3d 841 drivers/gpu/drm/v3d/v3d_gem.c mutex_init(&v3d->sched_lock); v3d 842 drivers/gpu/drm/v3d/v3d_gem.c mutex_init(&v3d->cache_clean_lock); v3d 848 drivers/gpu/drm/v3d/v3d_gem.c drm_mm_init(&v3d->mm, 1, pt_size / sizeof(u32) - 1); v3d 850 drivers/gpu/drm/v3d/v3d_gem.c v3d->pt = dma_alloc_wc(v3d->dev, pt_size, v3d 851 drivers/gpu/drm/v3d/v3d_gem.c &v3d->pt_paddr, v3d 853 drivers/gpu/drm/v3d/v3d_gem.c if (!v3d->pt) { v3d 854 drivers/gpu/drm/v3d/v3d_gem.c drm_mm_takedown(&v3d->mm); v3d 855 drivers/gpu/drm/v3d/v3d_gem.c dev_err(v3d->dev, v3d 861 drivers/gpu/drm/v3d/v3d_gem.c v3d_init_hw_state(v3d); v3d 862 drivers/gpu/drm/v3d/v3d_gem.c v3d_mmu_set_page_table(v3d); v3d 864 drivers/gpu/drm/v3d/v3d_gem.c ret = v3d_sched_init(v3d); v3d 866 drivers/gpu/drm/v3d/v3d_gem.c drm_mm_takedown(&v3d->mm); v3d 867 drivers/gpu/drm/v3d/v3d_gem.c dma_free_coherent(v3d->dev, 4096 * 1024, (void *)v3d->pt, v3d 868 drivers/gpu/drm/v3d/v3d_gem.c v3d->pt_paddr); v3d 877 drivers/gpu/drm/v3d/v3d_gem.c struct v3d_dev *v3d = to_v3d_dev(dev); v3d 879 drivers/gpu/drm/v3d/v3d_gem.c v3d_sched_fini(v3d); v3d 884 drivers/gpu/drm/v3d/v3d_gem.c WARN_ON(v3d->bin_job); v3d 885 drivers/gpu/drm/v3d/v3d_gem.c WARN_ON(v3d->render_job); v3d 887 drivers/gpu/drm/v3d/v3d_gem.c drm_mm_takedown(&v3d->mm); v3d 889 drivers/gpu/drm/v3d/v3d_gem.c dma_free_coherent(v3d->dev, 4096 * 1024, (void *)v3d->pt, v3d->pt_paddr); v3d 39 drivers/gpu/drm/v3d/v3d_irq.c struct v3d_dev *v3d = v3d 41 drivers/gpu/drm/v3d/v3d_irq.c struct drm_device *dev = &v3d->drm; v3d 61 drivers/gpu/drm/v3d/v3d_irq.c spin_lock_irqsave(&v3d->job_lock, irqflags); v3d 62 drivers/gpu/drm/v3d/v3d_irq.c if (!v3d->bin_job) { v3d 63 drivers/gpu/drm/v3d/v3d_irq.c spin_unlock_irqrestore(&v3d->job_lock, irqflags); v3d 68 drivers/gpu/drm/v3d/v3d_irq.c list_add_tail(&bo->unref_head, &v3d->bin_job->render->unref_list); v3d 69 drivers/gpu/drm/v3d/v3d_irq.c spin_unlock_irqrestore(&v3d->job_lock, irqflags); v3d 81 drivers/gpu/drm/v3d/v3d_irq.c struct v3d_dev *v3d = arg; v3d 96 drivers/gpu/drm/v3d/v3d_irq.c schedule_work(&v3d->overflow_mem_work); v3d 102 drivers/gpu/drm/v3d/v3d_irq.c to_v3d_fence(v3d->bin_job->base.irq_fence); v3d 104 drivers/gpu/drm/v3d/v3d_irq.c trace_v3d_bcl_irq(&v3d->drm, fence->seqno); v3d 111 drivers/gpu/drm/v3d/v3d_irq.c to_v3d_fence(v3d->render_job->base.irq_fence); v3d 113 drivers/gpu/drm/v3d/v3d_irq.c trace_v3d_rcl_irq(&v3d->drm, fence->seqno); v3d 120 drivers/gpu/drm/v3d/v3d_irq.c to_v3d_fence(v3d->csd_job->base.irq_fence); v3d 122 drivers/gpu/drm/v3d/v3d_irq.c trace_v3d_csd_irq(&v3d->drm, fence->seqno); v3d 131 drivers/gpu/drm/v3d/v3d_irq.c dev_err(v3d->dev, "GMP violation\n"); v3d 136 drivers/gpu/drm/v3d/v3d_irq.c if (v3d->single_irq_line && status == IRQ_NONE) v3d 145 drivers/gpu/drm/v3d/v3d_irq.c struct v3d_dev *v3d = arg; v3d 156 drivers/gpu/drm/v3d/v3d_irq.c to_v3d_fence(v3d->tfu_job->base.irq_fence); v3d 158 drivers/gpu/drm/v3d/v3d_irq.c trace_v3d_tfu_irq(&v3d->drm, fence->seqno); v3d 168 drivers/gpu/drm/v3d/v3d_irq.c (v3d->va_width - 32)); v3d 186 drivers/gpu/drm/v3d/v3d_irq.c if (v3d->ver >= 41) { v3d 192 drivers/gpu/drm/v3d/v3d_irq.c dev_err(v3d->dev, "MMU error from client %s (%d) at 0x%llx%s%s%s\n", v3d 207 drivers/gpu/drm/v3d/v3d_irq.c v3d_irq_init(struct v3d_dev *v3d) v3d 211 drivers/gpu/drm/v3d/v3d_irq.c INIT_WORK(&v3d->overflow_mem_work, v3d_overflow_mem_work); v3d 216 drivers/gpu/drm/v3d/v3d_irq.c for (core = 0; core < v3d->cores; core++) v3d 220 drivers/gpu/drm/v3d/v3d_irq.c irq1 = platform_get_irq(v3d->pdev, 1); v3d 224 drivers/gpu/drm/v3d/v3d_irq.c ret = devm_request_irq(v3d->dev, irq1, v3d 226 drivers/gpu/drm/v3d/v3d_irq.c "v3d_core0", v3d); v3d 229 drivers/gpu/drm/v3d/v3d_irq.c ret = devm_request_irq(v3d->dev, platform_get_irq(v3d->pdev, 0), v3d 231 drivers/gpu/drm/v3d/v3d_irq.c "v3d_hub", v3d); v3d 235 drivers/gpu/drm/v3d/v3d_irq.c v3d->single_irq_line = true; v3d 237 drivers/gpu/drm/v3d/v3d_irq.c ret = devm_request_irq(v3d->dev, platform_get_irq(v3d->pdev, 0), v3d 239 drivers/gpu/drm/v3d/v3d_irq.c "v3d", v3d); v3d 244 drivers/gpu/drm/v3d/v3d_irq.c v3d_irq_enable(v3d); v3d 249 drivers/gpu/drm/v3d/v3d_irq.c dev_err(v3d->dev, "IRQ setup failed: %d\n", ret); v3d 254 drivers/gpu/drm/v3d/v3d_irq.c v3d_irq_enable(struct v3d_dev *v3d) v3d 259 drivers/gpu/drm/v3d/v3d_irq.c for (core = 0; core < v3d->cores; core++) { v3d 269 drivers/gpu/drm/v3d/v3d_irq.c v3d_irq_disable(struct v3d_dev *v3d) v3d 274 drivers/gpu/drm/v3d/v3d_irq.c for (core = 0; core < v3d->cores; core++) v3d 279 drivers/gpu/drm/v3d/v3d_irq.c for (core = 0; core < v3d->cores; core++) v3d 283 drivers/gpu/drm/v3d/v3d_irq.c cancel_work_sync(&v3d->overflow_mem_work); v3d 287 drivers/gpu/drm/v3d/v3d_irq.c void v3d_irq_reset(struct v3d_dev *v3d) v3d 289 drivers/gpu/drm/v3d/v3d_irq.c v3d_irq_enable(v3d); v3d 33 drivers/gpu/drm/v3d/v3d_mmu.c static int v3d_mmu_flush_all(struct v3d_dev *v3d) v3d 43 drivers/gpu/drm/v3d/v3d_mmu.c dev_err(v3d->dev, "TLB clear wait idle pre-wait failed\n"); v3d 55 drivers/gpu/drm/v3d/v3d_mmu.c dev_err(v3d->dev, "TLB clear wait idle failed\n"); v3d 62 drivers/gpu/drm/v3d/v3d_mmu.c dev_err(v3d->dev, "MMUC flush wait idle failed\n"); v3d 67 drivers/gpu/drm/v3d/v3d_mmu.c int v3d_mmu_set_page_table(struct v3d_dev *v3d) v3d 69 drivers/gpu/drm/v3d/v3d_mmu.c V3D_WRITE(V3D_MMU_PT_PA_BASE, v3d->pt_paddr >> V3D_MMU_PAGE_SHIFT); v3d 80 drivers/gpu/drm/v3d/v3d_mmu.c (v3d->mmu_scratch_paddr >> V3D_MMU_PAGE_SHIFT) | v3d 84 drivers/gpu/drm/v3d/v3d_mmu.c return v3d_mmu_flush_all(v3d); v3d 90 drivers/gpu/drm/v3d/v3d_mmu.c struct v3d_dev *v3d = to_v3d_dev(shmem_obj->base.dev); v3d 105 drivers/gpu/drm/v3d/v3d_mmu.c v3d->pt[page++] = pte + i; v3d 111 drivers/gpu/drm/v3d/v3d_mmu.c if (v3d_mmu_flush_all(v3d)) v3d 112 drivers/gpu/drm/v3d/v3d_mmu.c dev_err(v3d->dev, "MMU flush timeout\n"); v3d 117 drivers/gpu/drm/v3d/v3d_mmu.c struct v3d_dev *v3d = to_v3d_dev(bo->base.base.dev); v3d 122 drivers/gpu/drm/v3d/v3d_mmu.c v3d->pt[page] = 0; v3d 124 drivers/gpu/drm/v3d/v3d_mmu.c if (v3d_mmu_flush_all(v3d)) v3d 125 drivers/gpu/drm/v3d/v3d_mmu.c dev_err(v3d->dev, "MMU flush timeout\n"); v3d 91 drivers/gpu/drm/v3d/v3d_sched.c struct v3d_dev *v3d = job->base.v3d; v3d 92 drivers/gpu/drm/v3d/v3d_sched.c struct drm_device *dev = &v3d->drm; v3d 102 drivers/gpu/drm/v3d/v3d_sched.c spin_lock_irqsave(&v3d->job_lock, irqflags); v3d 103 drivers/gpu/drm/v3d/v3d_sched.c v3d->bin_job = job; v3d 108 drivers/gpu/drm/v3d/v3d_sched.c spin_unlock_irqrestore(&v3d->job_lock, irqflags); v3d 110 drivers/gpu/drm/v3d/v3d_sched.c v3d_invalidate_caches(v3d); v3d 112 drivers/gpu/drm/v3d/v3d_sched.c fence = v3d_fence_create(v3d, V3D_BIN); v3d 144 drivers/gpu/drm/v3d/v3d_sched.c struct v3d_dev *v3d = job->base.v3d; v3d 145 drivers/gpu/drm/v3d/v3d_sched.c struct drm_device *dev = &v3d->drm; v3d 151 drivers/gpu/drm/v3d/v3d_sched.c v3d->render_job = job; v3d 159 drivers/gpu/drm/v3d/v3d_sched.c v3d_invalidate_caches(v3d); v3d 161 drivers/gpu/drm/v3d/v3d_sched.c fence = v3d_fence_create(v3d, V3D_RENDER); v3d 187 drivers/gpu/drm/v3d/v3d_sched.c struct v3d_dev *v3d = job->base.v3d; v3d 188 drivers/gpu/drm/v3d/v3d_sched.c struct drm_device *dev = &v3d->drm; v3d 191 drivers/gpu/drm/v3d/v3d_sched.c fence = v3d_fence_create(v3d, V3D_TFU); v3d 195 drivers/gpu/drm/v3d/v3d_sched.c v3d->tfu_job = job; v3d 224 drivers/gpu/drm/v3d/v3d_sched.c struct v3d_dev *v3d = job->base.v3d; v3d 225 drivers/gpu/drm/v3d/v3d_sched.c struct drm_device *dev = &v3d->drm; v3d 229 drivers/gpu/drm/v3d/v3d_sched.c v3d->csd_job = job; v3d 231 drivers/gpu/drm/v3d/v3d_sched.c v3d_invalidate_caches(v3d); v3d 233 drivers/gpu/drm/v3d/v3d_sched.c fence = v3d_fence_create(v3d, V3D_CSD); v3d 255 drivers/gpu/drm/v3d/v3d_sched.c struct v3d_dev *v3d = job->v3d; v3d 257 drivers/gpu/drm/v3d/v3d_sched.c v3d_clean_caches(v3d); v3d 263 drivers/gpu/drm/v3d/v3d_sched.c v3d_gpu_reset_for_timeout(struct v3d_dev *v3d, struct drm_sched_job *sched_job) v3d 267 drivers/gpu/drm/v3d/v3d_sched.c mutex_lock(&v3d->reset_lock); v3d 271 drivers/gpu/drm/v3d/v3d_sched.c drm_sched_stop(&v3d->queue[q].sched, sched_job); v3d 277 drivers/gpu/drm/v3d/v3d_sched.c v3d_reset(v3d); v3d 280 drivers/gpu/drm/v3d/v3d_sched.c drm_sched_resubmit_jobs(&v3d->queue[q].sched); v3d 284 drivers/gpu/drm/v3d/v3d_sched.c drm_sched_start(&v3d->queue[q].sched, true); v3d 287 drivers/gpu/drm/v3d/v3d_sched.c mutex_unlock(&v3d->reset_lock); v3d 300 drivers/gpu/drm/v3d/v3d_sched.c struct v3d_dev *v3d = job->v3d; v3d 310 drivers/gpu/drm/v3d/v3d_sched.c v3d_gpu_reset_for_timeout(v3d, sched_job); v3d 336 drivers/gpu/drm/v3d/v3d_sched.c v3d_gpu_reset_for_timeout(job->v3d, sched_job); v3d 343 drivers/gpu/drm/v3d/v3d_sched.c struct v3d_dev *v3d = job->base.v3d; v3d 354 drivers/gpu/drm/v3d/v3d_sched.c v3d_gpu_reset_for_timeout(v3d, sched_job); v3d 393 drivers/gpu/drm/v3d/v3d_sched.c v3d_sched_init(struct v3d_dev *v3d) v3d 400 drivers/gpu/drm/v3d/v3d_sched.c ret = drm_sched_init(&v3d->queue[V3D_BIN].sched, v3d 406 drivers/gpu/drm/v3d/v3d_sched.c dev_err(v3d->dev, "Failed to create bin scheduler: %d.", ret); v3d 410 drivers/gpu/drm/v3d/v3d_sched.c ret = drm_sched_init(&v3d->queue[V3D_RENDER].sched, v3d 416 drivers/gpu/drm/v3d/v3d_sched.c dev_err(v3d->dev, "Failed to create render scheduler: %d.", v3d 418 drivers/gpu/drm/v3d/v3d_sched.c v3d_sched_fini(v3d); v3d 422 drivers/gpu/drm/v3d/v3d_sched.c ret = drm_sched_init(&v3d->queue[V3D_TFU].sched, v3d 428 drivers/gpu/drm/v3d/v3d_sched.c dev_err(v3d->dev, "Failed to create TFU scheduler: %d.", v3d 430 drivers/gpu/drm/v3d/v3d_sched.c v3d_sched_fini(v3d); v3d 434 drivers/gpu/drm/v3d/v3d_sched.c if (v3d_has_csd(v3d)) { v3d 435 drivers/gpu/drm/v3d/v3d_sched.c ret = drm_sched_init(&v3d->queue[V3D_CSD].sched, v3d 441 drivers/gpu/drm/v3d/v3d_sched.c dev_err(v3d->dev, "Failed to create CSD scheduler: %d.", v3d 443 drivers/gpu/drm/v3d/v3d_sched.c v3d_sched_fini(v3d); v3d 447 drivers/gpu/drm/v3d/v3d_sched.c ret = drm_sched_init(&v3d->queue[V3D_CACHE_CLEAN].sched, v3d 453 drivers/gpu/drm/v3d/v3d_sched.c dev_err(v3d->dev, "Failed to create CACHE_CLEAN scheduler: %d.", v3d 455 drivers/gpu/drm/v3d/v3d_sched.c v3d_sched_fini(v3d); v3d 464 drivers/gpu/drm/v3d/v3d_sched.c v3d_sched_fini(struct v3d_dev *v3d) v3d 469 drivers/gpu/drm/v3d/v3d_sched.c if (v3d->queue[q].sched.ready) v3d 470 drivers/gpu/drm/v3d/v3d_sched.c drm_sched_fini(&v3d->queue[q].sched); v3d 12 drivers/gpu/drm/v3d/v3d_trace.h #define TRACE_SYSTEM v3d v3d 800 drivers/gpu/drm/vc4/vc4_bo.c if (!vc4->v3d) v3d 77 drivers/gpu/drm/vc4/vc4_drv.c if (!vc4->v3d) v3d 76 drivers/gpu/drm/vc4/vc4_drv.h struct vc4_v3d *v3d; v3d 478 drivers/gpu/drm/vc4/vc4_drv.h #define V3D_READ(offset) readl(vc4->v3d->regs + offset) v3d 479 drivers/gpu/drm/vc4/vc4_drv.h #define V3D_WRITE(offset, val) writel(val, vc4->v3d->regs + offset) v3d 79 drivers/gpu/drm/vc4/vc4_gem.c if (!vc4->v3d) { v3d 297 drivers/gpu/drm/vc4/vc4_gem.c pm_runtime_put_sync_suspend(&vc4->v3d->pdev->dev); v3d 298 drivers/gpu/drm/vc4/vc4_gem.c pm_runtime_get_sync(&vc4->v3d->pdev->dev); v3d 1140 drivers/gpu/drm/vc4/vc4_gem.c if (!vc4->v3d) { v3d 242 drivers/gpu/drm/vc4/vc4_irq.c if (!vc4->v3d) v3d 259 drivers/gpu/drm/vc4/vc4_irq.c if (!vc4->v3d) v3d 275 drivers/gpu/drm/vc4/vc4_irq.c if (!vc4->v3d) v3d 110 drivers/gpu/drm/vc4/vc4_perfmon.c if (!vc4->v3d) { v3d 160 drivers/gpu/drm/vc4/vc4_perfmon.c if (!vc4->v3d) { v3d 185 drivers/gpu/drm/vc4/vc4_perfmon.c if (!vc4->v3d) { v3d 134 drivers/gpu/drm/vc4/vc4_v3d.c int ret = pm_runtime_get_sync(&vc4->v3d->pdev->dev); v3d 152 drivers/gpu/drm/vc4/vc4_v3d.c pm_runtime_mark_last_busy(&vc4->v3d->pdev->dev); v3d 153 drivers/gpu/drm/vc4/vc4_v3d.c pm_runtime_put_autosuspend(&vc4->v3d->pdev->dev); v3d 232 drivers/gpu/drm/vc4/vc4_v3d.c struct vc4_v3d *v3d = vc4->v3d; v3d 237 drivers/gpu/drm/vc4/vc4_v3d.c if (!v3d) v3d 255 drivers/gpu/drm/vc4/vc4_v3d.c dev_err(&v3d->pdev->dev, v3d 361 drivers/gpu/drm/vc4/vc4_v3d.c struct vc4_v3d *v3d = dev_get_drvdata(dev); v3d 362 drivers/gpu/drm/vc4/vc4_v3d.c struct vc4_dev *vc4 = v3d->vc4; v3d 366 drivers/gpu/drm/vc4/vc4_v3d.c clk_disable_unprepare(v3d->clk); v3d 373 drivers/gpu/drm/vc4/vc4_v3d.c struct vc4_v3d *v3d = dev_get_drvdata(dev); v3d 374 drivers/gpu/drm/vc4/vc4_v3d.c struct vc4_dev *vc4 = v3d->vc4; v3d 377 drivers/gpu/drm/vc4/vc4_v3d.c ret = clk_prepare_enable(v3d->clk); v3d 396 drivers/gpu/drm/vc4/vc4_v3d.c struct vc4_v3d *v3d = NULL; v3d 399 drivers/gpu/drm/vc4/vc4_v3d.c v3d = devm_kzalloc(&pdev->dev, sizeof(*v3d), GFP_KERNEL); v3d 400 drivers/gpu/drm/vc4/vc4_v3d.c if (!v3d) v3d 403 drivers/gpu/drm/vc4/vc4_v3d.c dev_set_drvdata(dev, v3d); v3d 405 drivers/gpu/drm/vc4/vc4_v3d.c v3d->pdev = pdev; v3d 407 drivers/gpu/drm/vc4/vc4_v3d.c v3d->regs = vc4_ioremap_regs(pdev, 0); v3d 408 drivers/gpu/drm/vc4/vc4_v3d.c if (IS_ERR(v3d->regs)) v3d 409 drivers/gpu/drm/vc4/vc4_v3d.c return PTR_ERR(v3d->regs); v3d 410 drivers/gpu/drm/vc4/vc4_v3d.c v3d->regset.base = v3d->regs; v3d 411 drivers/gpu/drm/vc4/vc4_v3d.c v3d->regset.regs = v3d_regs; v3d 412 drivers/gpu/drm/vc4/vc4_v3d.c v3d->regset.nregs = ARRAY_SIZE(v3d_regs); v3d 414 drivers/gpu/drm/vc4/vc4_v3d.c vc4->v3d = v3d; v3d 415 drivers/gpu/drm/vc4/vc4_v3d.c v3d->vc4 = vc4; v3d 417 drivers/gpu/drm/vc4/vc4_v3d.c v3d->clk = devm_clk_get(dev, NULL); v3d 418 drivers/gpu/drm/vc4/vc4_v3d.c if (IS_ERR(v3d->clk)) { v3d 419 drivers/gpu/drm/vc4/vc4_v3d.c int ret = PTR_ERR(v3d->clk); v3d 424 drivers/gpu/drm/vc4/vc4_v3d.c v3d->clk = NULL; v3d 439 drivers/gpu/drm/vc4/vc4_v3d.c ret = clk_prepare_enable(v3d->clk); v3d 463 drivers/gpu/drm/vc4/vc4_v3d.c vc4_debugfs_add_regset32(drm, "v3d_regs", &v3d->regset); v3d 485 drivers/gpu/drm/vc4/vc4_v3d.c vc4->v3d = NULL;