uvd_dpm_enable_mask  163 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h 	uint32_t  uvd_dpm_enable_mask;
uvd_dpm_enable_mask  173 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h 	uint32_t  uvd_dpm_enable_mask;
uvd_dpm_enable_mask  152 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h 	uint32_t  uvd_dpm_enable_mask;
uvd_dpm_enable_mask  205 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h 	uint32_t  uvd_dpm_enable_mask;
uvd_dpm_enable_mask 2876 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	data->dpm_level_enable_mask.uvd_dpm_enable_mask = 0;
uvd_dpm_enable_mask 2880 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 			data->dpm_level_enable_mask.uvd_dpm_enable_mask |= 1 << i;
uvd_dpm_enable_mask 2885 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 				data->dpm_level_enable_mask.uvd_dpm_enable_mask);
uvd_dpm_enable_mask 3943 drivers/gpu/drm/radeon/ci_dpm.c 		pi->dpm_level_enable_mask.uvd_dpm_enable_mask = 0;
uvd_dpm_enable_mask 3947 drivers/gpu/drm/radeon/ci_dpm.c 				pi->dpm_level_enable_mask.uvd_dpm_enable_mask |= 1 << i;
uvd_dpm_enable_mask 3956 drivers/gpu/drm/radeon/ci_dpm.c 						  pi->dpm_level_enable_mask.uvd_dpm_enable_mask);
uvd_dpm_enable_mask  107 drivers/gpu/drm/radeon/ci_dpm.h 	u32 uvd_dpm_enable_mask;