uvd 932 drivers/gpu/drm/amd/amdgpu/amdgpu.h struct amdgpu_uvd uvd; uvd 145 drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c rings[0] = &adev->uvd.inst[0].ring; uvd 153 drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c rings[0] = &adev->uvd.inst[0].ring_enc[0]; uvd 402 drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c index = ALIGN(adev->uvd.fw->size, 8); uvd 403 drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c ring->fence_drv.cpu_addr = adev->uvd.inst[ring->me].cpu_addr + index; uvd 404 drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c ring->fence_drv.gpu_addr = adev->uvd.inst[ring->me].gpu_addr + index; uvd 214 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c fw_info->ver = adev->uvd.fw_version; uvd 342 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c for (i = 0; i < adev->uvd.num_uvd_inst; i++) { uvd 343 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c if (adev->uvd.harvest_config & (1 << i)) uvd 346 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c if (adev->uvd.inst[i].ring.sched.ready) uvd 362 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c for (i = 0; i < adev->uvd.num_uvd_inst; i++) { uvd 363 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c if (adev->uvd.harvest_config & (1 << i)) uvd 366 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c for (j = 0; j < adev->uvd.num_enc_rings; j++) uvd 367 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c if (adev->uvd.inst[i].ring_enc[j].sched.ready) uvd 376 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c if (adev->uvd.harvest_config & (1 << i)) uvd 388 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c if (adev->uvd.harvest_config & (1 << i)) uvd 401 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c if (adev->uvd.harvest_config & (1 << i)) uvd 814 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c handle.uvd_max_handles = adev->uvd.max_handles; uvd 2678 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c adev->uvd.decode_image_width >= WIDTH_4K) { uvd 394 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c FW_VERSION_ATTR(uvd_fw_version, 0444, uvd.fw_version); uvd 131 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c INIT_DELAYED_WORK(&adev->uvd.idle_work, amdgpu_uvd_idle_work_handler); uvd 188 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c r = request_firmware(&adev->uvd.fw, fw_name, adev->dev); uvd 195 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c r = amdgpu_ucode_validate(adev->uvd.fw); uvd 199 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c release_firmware(adev->uvd.fw); uvd 200 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c adev->uvd.fw = NULL; uvd 205 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c adev->uvd.max_handles = AMDGPU_DEFAULT_UVD_HANDLES; uvd 207 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c hdr = (const struct common_firmware_header *)adev->uvd.fw->data; uvd 226 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c adev->uvd.max_handles = AMDGPU_MAX_UVD_HANDLES; uvd 228 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c adev->uvd.fw_version = ((version_major << 24) | (version_minor << 16) | uvd 233 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c (adev->uvd.fw_version < FW_1_66_16)) uvd 245 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c adev->uvd.max_handles = AMDGPU_MAX_UVD_HANDLES; uvd 247 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c adev->uvd.fw_version = le32_to_cpu(hdr->ucode_version); uvd 251 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c + AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles; uvd 255 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c for (j = 0; j < adev->uvd.num_uvd_inst; j++) { uvd 256 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c if (adev->uvd.harvest_config & (1 << j)) uvd 259 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c AMDGPU_GEM_DOMAIN_VRAM, &adev->uvd.inst[j].vcpu_bo, uvd 260 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c &adev->uvd.inst[j].gpu_addr, &adev->uvd.inst[j].cpu_addr); uvd 267 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c for (i = 0; i < adev->uvd.max_handles; ++i) { uvd 268 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c atomic_set(&adev->uvd.handles[i], 0); uvd 269 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c adev->uvd.filp[i] = NULL; uvd 274 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c adev->uvd.address_64_bit = true; uvd 278 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_65_10; uvd 281 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_87_11; uvd 284 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_87_12; uvd 287 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_37_15; uvd 290 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c adev->uvd.use_ctx_buf = adev->asic_type >= CHIP_POLARIS10; uvd 300 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c drm_sched_entity_destroy(&adev->uvd.entity); uvd 302 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c for (j = 0; j < adev->uvd.num_uvd_inst; ++j) { uvd 303 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c if (adev->uvd.harvest_config & (1 << j)) uvd 305 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c kvfree(adev->uvd.inst[j].saved_bo); uvd 307 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c amdgpu_bo_free_kernel(&adev->uvd.inst[j].vcpu_bo, uvd 308 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c &adev->uvd.inst[j].gpu_addr, uvd 309 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c (void **)&adev->uvd.inst[j].cpu_addr); uvd 311 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c amdgpu_ring_fini(&adev->uvd.inst[j].ring); uvd 314 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c amdgpu_ring_fini(&adev->uvd.inst[j].ring_enc[i]); uvd 316 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c release_firmware(adev->uvd.fw); uvd 333 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c ring = &adev->uvd.inst[0].ring; uvd 335 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c r = drm_sched_entity_init(&adev->uvd.entity, &rq, 1, NULL); uvd 350 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c cancel_delayed_work_sync(&adev->uvd.idle_work); uvd 354 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c for (i = 0; i < adev->uvd.max_handles; ++i) uvd 355 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c if (atomic_read(&adev->uvd.handles[i])) uvd 358 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c if (i == adev->uvd.max_handles) uvd 362 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c for (j = 0; j < adev->uvd.num_uvd_inst; ++j) { uvd 363 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c if (adev->uvd.harvest_config & (1 << j)) uvd 365 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c if (adev->uvd.inst[j].vcpu_bo == NULL) uvd 368 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c size = amdgpu_bo_size(adev->uvd.inst[j].vcpu_bo); uvd 369 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c ptr = adev->uvd.inst[j].cpu_addr; uvd 371 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c adev->uvd.inst[j].saved_bo = kvmalloc(size, GFP_KERNEL); uvd 372 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c if (!adev->uvd.inst[j].saved_bo) uvd 375 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c memcpy_fromio(adev->uvd.inst[j].saved_bo, ptr, size); uvd 386 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c for (i = 0; i < adev->uvd.num_uvd_inst; i++) { uvd 387 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c if (adev->uvd.harvest_config & (1 << i)) uvd 389 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c if (adev->uvd.inst[i].vcpu_bo == NULL) uvd 392 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c size = amdgpu_bo_size(adev->uvd.inst[i].vcpu_bo); uvd 393 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c ptr = adev->uvd.inst[i].cpu_addr; uvd 395 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c if (adev->uvd.inst[i].saved_bo != NULL) { uvd 396 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c memcpy_toio(ptr, adev->uvd.inst[i].saved_bo, size); uvd 397 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c kvfree(adev->uvd.inst[i].saved_bo); uvd 398 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c adev->uvd.inst[i].saved_bo = NULL; uvd 403 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c hdr = (const struct common_firmware_header *)adev->uvd.fw->data; uvd 406 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c memcpy_toio(adev->uvd.inst[i].cpu_addr, adev->uvd.fw->data + offset, uvd 413 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c amdgpu_fence_driver_force_completion(&adev->uvd.inst[i].ring); uvd 421 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c struct amdgpu_ring *ring = &adev->uvd.inst[0].ring; uvd 424 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c for (i = 0; i < adev->uvd.max_handles; ++i) { uvd 425 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c uint32_t handle = atomic_read(&adev->uvd.handles[i]); uvd 427 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c if (handle != 0 && adev->uvd.filp[i] == filp) { uvd 440 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c adev->uvd.filp[i] = NULL; uvd 441 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c atomic_set(&adev->uvd.handles[i], 0); uvd 490 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c if (!ctx->parser->adev->uvd.address_64_bit) { uvd 648 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c if (!adev->uvd.use_ctx_buf){ uvd 696 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c adev->uvd.decode_image_width = width; uvd 746 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c for (i = 0; i < adev->uvd.max_handles; ++i) { uvd 747 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c if (atomic_read(&adev->uvd.handles[i]) == handle) { uvd 753 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c if (!atomic_cmpxchg(&adev->uvd.handles[i], 0, handle)) { uvd 754 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c adev->uvd.filp[i] = ctx->parser->filp; uvd 770 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c for (i = 0; i < adev->uvd.max_handles; ++i) { uvd 771 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c if (atomic_read(&adev->uvd.handles[i]) == handle) { uvd 772 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c if (adev->uvd.filp[i] != ctx->parser->filp) { uvd 785 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c for (i = 0; i < adev->uvd.max_handles; ++i) uvd 786 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c atomic_cmpxchg(&adev->uvd.handles[i], handle, 0); uvd 854 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c if (!ctx->parser->adev->uvd.address_64_bit) { uvd 862 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c (start >> 28) != (ctx->parser->adev->uvd.inst->gpu_addr >> 28)) { uvd 999 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c if (!parser->adev->uvd.address_64_bit) { uvd 1036 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c if (!ring->adev->uvd.address_64_bit) { uvd 1093 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c r = amdgpu_job_submit(job, &adev->uvd.entity, uvd 1181 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c container_of(work, struct amdgpu_device, uvd.idle_work.work); uvd 1184 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c for (i = 0; i < adev->uvd.num_uvd_inst; ++i) { uvd 1185 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c if (adev->uvd.harvest_config & (1 << i)) uvd 1187 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c fences += amdgpu_fence_count_emitted(&adev->uvd.inst[i].ring); uvd 1188 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c for (j = 0; j < adev->uvd.num_enc_rings; ++j) { uvd 1189 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c fences += amdgpu_fence_count_emitted(&adev->uvd.inst[i].ring_enc[j]); uvd 1205 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c schedule_delayed_work(&adev->uvd.idle_work, UVD_IDLE_TIMEOUT); uvd 1217 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c set_clocks = !cancel_delayed_work_sync(&adev->uvd.idle_work); uvd 1234 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c schedule_delayed_work(&ring->adev->uvd.idle_work, UVD_IDLE_TIMEOUT); uvd 1281 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c for (i = 0; i < adev->uvd.max_handles; ++i) { uvd 1287 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c if (atomic_read(&adev->uvd.handles[i])) uvd 37 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h (AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(((const struct common_firmware_header *)(adev)->uvd.fw->data)->ucode_size_bytes) + \ uvd 96 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c adev->uvd.num_uvd_inst = 1; uvd 111 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 124, &adev->uvd.inst->irq); uvd 119 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c ring = &adev->uvd.inst->ring; uvd 121 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst->irq, 0); uvd 158 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c struct amdgpu_ring *ring = &adev->uvd.inst->ring; uvd 213 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c struct amdgpu_ring *ring = &adev->uvd.inst->ring; uvd 256 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c struct amdgpu_ring *ring = &adev->uvd.inst->ring; uvd 547 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c addr = (adev->uvd.inst->gpu_addr + AMDGPU_UVD_FIRMWARE_OFFSET) >> 3; uvd 559 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles)) >> 3; uvd 564 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c addr = (adev->uvd.inst->gpu_addr >> 28) & 0xF; uvd 568 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c addr = (adev->uvd.inst->gpu_addr >> 32) & 0xFF; uvd 675 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c amdgpu_fence_process(&adev->uvd.inst->ring); uvd 764 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c adev->uvd.inst->ring.funcs = &uvd_v4_2_ring_funcs; uvd 774 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c adev->uvd.inst->irq.num_types = 1; uvd 775 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c adev->uvd.inst->irq.funcs = &uvd_v4_2_irq_funcs; uvd 94 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c adev->uvd.num_uvd_inst = 1; uvd 109 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_UVD_SYSTEM_MESSAGE, &adev->uvd.inst->irq); uvd 117 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c ring = &adev->uvd.inst->ring; uvd 119 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst->irq, 0); uvd 154 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c struct amdgpu_ring *ring = &adev->uvd.inst->ring; uvd 211 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c struct amdgpu_ring *ring = &adev->uvd.inst->ring; uvd 260 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c lower_32_bits(adev->uvd.inst->gpu_addr)); uvd 262 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c upper_32_bits(adev->uvd.inst->gpu_addr)); uvd 276 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles); uvd 294 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c struct amdgpu_ring *ring = &adev->uvd.inst->ring; uvd 598 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c amdgpu_fence_process(&adev->uvd.inst->ring); uvd 873 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c adev->uvd.inst->ring.funcs = &uvd_v5_0_ring_funcs; uvd 883 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c adev->uvd.inst->irq.num_types = 1; uvd 884 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c adev->uvd.inst->irq.funcs = &uvd_v5_0_irq_funcs; uvd 67 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c (!adev->uvd.fw_version || adev->uvd.fw_version >= FW_1_130_16)); uvd 95 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c if (ring == &adev->uvd.inst->ring_enc[0]) uvd 125 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c if (ring == &adev->uvd.inst->ring_enc[0]) uvd 156 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c if (ring == &adev->uvd.inst->ring_enc[0]) uvd 365 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c adev->uvd.num_uvd_inst = 1; uvd 374 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c adev->uvd.num_enc_rings = 2; uvd 390 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_UVD_SYSTEM_MESSAGE, &adev->uvd.inst->irq); uvd 396 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c for (i = 0; i < adev->uvd.num_enc_rings; ++i) { uvd 397 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i + VISLANDS30_IV_SRCID_UVD_ENC_GEN_PURP, &adev->uvd.inst->irq); uvd 408 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c for (i = 0; i < adev->uvd.num_enc_rings; ++i) uvd 409 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c adev->uvd.inst->ring_enc[i].funcs = NULL; uvd 411 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c adev->uvd.inst->irq.num_types = 1; uvd 412 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c adev->uvd.num_enc_rings = 0; uvd 417 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c ring = &adev->uvd.inst->ring; uvd 419 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst->irq, 0); uvd 428 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c for (i = 0; i < adev->uvd.num_enc_rings; ++i) { uvd 429 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c ring = &adev->uvd.inst->ring_enc[i]; uvd 431 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst->irq, 0); uvd 452 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c for (i = 0; i < adev->uvd.num_enc_rings; ++i) uvd 453 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c amdgpu_ring_fini(&adev->uvd.inst->ring_enc[i]); uvd 469 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c struct amdgpu_ring *ring = &adev->uvd.inst->ring; uvd 509 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c for (i = 0; i < adev->uvd.num_enc_rings; ++i) { uvd 510 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c ring = &adev->uvd.inst->ring_enc[i]; uvd 538 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c struct amdgpu_ring *ring = &adev->uvd.inst->ring; uvd 586 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c lower_32_bits(adev->uvd.inst->gpu_addr)); uvd 588 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c upper_32_bits(adev->uvd.inst->gpu_addr)); uvd 602 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles); uvd 610 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c WREG32(mmUVD_GP_SCRATCH4, adev->uvd.max_handles); uvd 701 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c struct amdgpu_ring *ring = &adev->uvd.inst->ring; uvd 841 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c ring = &adev->uvd.inst->ring_enc[0]; uvd 848 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c ring = &adev->uvd.inst->ring_enc[1]; uvd 1145 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c adev->uvd.inst->srbm_soft_reset = srbm_soft_reset; uvd 1148 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c adev->uvd.inst->srbm_soft_reset = 0; uvd 1157 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c if (!adev->uvd.inst->srbm_soft_reset) uvd 1169 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c if (!adev->uvd.inst->srbm_soft_reset) uvd 1171 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c srbm_soft_reset = adev->uvd.inst->srbm_soft_reset; uvd 1199 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c if (!adev->uvd.inst->srbm_soft_reset) uvd 1225 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c amdgpu_fence_process(&adev->uvd.inst->ring); uvd 1229 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c amdgpu_fence_process(&adev->uvd.inst->ring_enc[0]); uvd 1235 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c amdgpu_fence_process(&adev->uvd.inst->ring_enc[1]); uvd 1600 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c adev->uvd.inst->ring.funcs = &uvd_v6_0_ring_vm_funcs; uvd 1603 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c adev->uvd.inst->ring.funcs = &uvd_v6_0_ring_phys_funcs; uvd 1612 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c for (i = 0; i < adev->uvd.num_enc_rings; ++i) uvd 1613 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c adev->uvd.inst->ring_enc[i].funcs = &uvd_v6_0_enc_ring_vm_funcs; uvd 1626 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c adev->uvd.inst->irq.num_types = adev->uvd.num_enc_rings + 1; uvd 1628 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c adev->uvd.inst->irq.num_types = 1; uvd 1630 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c adev->uvd.inst->irq.funcs = &uvd_v6_0_irq_funcs; uvd 89 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c if (ring == &adev->uvd.inst[ring->me].ring_enc[0]) uvd 123 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c if (ring == &adev->uvd.inst[ring->me].ring_enc[0]) uvd 161 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c if (ring == &adev->uvd.inst[ring->me].ring_enc[0]) uvd 377 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c adev->uvd.num_uvd_inst = UVD7_MAX_HW_INSTANCES_VEGA20; uvd 378 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c for (i = 0; i < adev->uvd.num_uvd_inst; i++) { uvd 381 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c adev->uvd.harvest_config |= 1 << i; uvd 384 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c if (adev->uvd.harvest_config == (AMDGPU_UVD_HARVEST_UVD0 | uvd 389 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c adev->uvd.num_uvd_inst = 1; uvd 393 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c adev->uvd.num_enc_rings = 1; uvd 395 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c adev->uvd.num_enc_rings = 2; uvd 410 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c for (j = 0; j < adev->uvd.num_uvd_inst; j++) { uvd 411 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c if (adev->uvd.harvest_config & (1 << j)) uvd 414 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_uvds[j], UVD_7_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->uvd.inst[j].irq); uvd 419 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c for (i = 0; i < adev->uvd.num_enc_rings; ++i) { uvd 420 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_uvds[j], i + UVD_7_0__SRCID__UVD_ENC_GEN_PURP, &adev->uvd.inst[j].irq); uvd 432 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c hdr = (const struct common_firmware_header *)adev->uvd.fw->data; uvd 434 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].fw = adev->uvd.fw; uvd 438 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c if (adev->uvd.num_uvd_inst == UVD7_MAX_HW_INSTANCES_VEGA20) { uvd 440 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c adev->firmware.ucode[AMDGPU_UCODE_ID_UVD1].fw = adev->uvd.fw; uvd 447 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c for (j = 0; j < adev->uvd.num_uvd_inst; j++) { uvd 448 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c if (adev->uvd.harvest_config & (1 << j)) uvd 451 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c ring = &adev->uvd.inst[j].ring; uvd 453 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst[j].irq, 0); uvd 458 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c for (i = 0; i < adev->uvd.num_enc_rings; ++i) { uvd 459 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c ring = &adev->uvd.inst[j].ring_enc[i]; uvd 472 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst[j].irq, 0); uvd 504 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c for (j = 0; j < adev->uvd.num_uvd_inst; ++j) { uvd 505 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c if (adev->uvd.harvest_config & (1 << j)) uvd 507 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c for (i = 0; i < adev->uvd.num_enc_rings; ++i) uvd 508 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c amdgpu_ring_fini(&adev->uvd.inst[j].ring_enc[i]); uvd 534 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c for (j = 0; j < adev->uvd.num_uvd_inst; ++j) { uvd 535 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c if (adev->uvd.harvest_config & (1 << j)) uvd 537 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c ring = &adev->uvd.inst[j].ring; uvd 577 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c for (i = 0; i < adev->uvd.num_enc_rings; ++i) { uvd 578 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c ring = &adev->uvd.inst[j].ring_enc[i]; uvd 610 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c for (i = 0; i < adev->uvd.num_uvd_inst; ++i) { uvd 611 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c if (adev->uvd.harvest_config & (1 << i)) uvd 613 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c adev->uvd.inst[i].ring.sched.ready = false; uvd 656 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c for (i = 0; i < adev->uvd.num_uvd_inst; ++i) { uvd 657 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c if (adev->uvd.harvest_config & (1 << i)) uvd 672 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c lower_32_bits(adev->uvd.inst[i].gpu_addr)); uvd 674 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c upper_32_bits(adev->uvd.inst[i].gpu_addr)); uvd 683 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c lower_32_bits(adev->uvd.inst[i].gpu_addr + offset)); uvd 685 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c upper_32_bits(adev->uvd.inst[i].gpu_addr + offset)); uvd 690 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c lower_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE)); uvd 692 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c upper_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE)); uvd 704 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, i, mmUVD_GP_SCRATCH4, adev->uvd.max_handles); uvd 735 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c for (i = 0; i < adev->uvd.num_uvd_inst; ++i) { uvd 736 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c if (adev->uvd.harvest_config & (1 << i)) uvd 738 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WDOORBELL32(adev->uvd.inst[i].ring_enc[0].doorbell_index, 0); uvd 739 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c adev->wb.wb[adev->uvd.inst[i].ring_enc[0].wptr_offs] = 0; uvd 740 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c adev->uvd.inst[i].ring_enc[0].wptr = 0; uvd 741 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c adev->uvd.inst[i].ring_enc[0].wptr_old = 0; uvd 793 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c for (i = 0; i < adev->uvd.num_uvd_inst; ++i) { uvd 794 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c if (adev->uvd.harvest_config & (1 << i)) uvd 796 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c ring = &adev->uvd.inst[i].ring; uvd 798 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4); uvd 814 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c lower_32_bits(adev->uvd.inst[i].gpu_addr)); uvd 816 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c upper_32_bits(adev->uvd.inst[i].gpu_addr)); uvd 826 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c lower_32_bits(adev->uvd.inst[i].gpu_addr + offset)); uvd 828 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c upper_32_bits(adev->uvd.inst[i].gpu_addr + offset)); uvd 833 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c lower_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE)); uvd 835 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c upper_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE)); uvd 840 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_GP_SCRATCH4), adev->uvd.max_handles); uvd 899 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c ring = &adev->uvd.inst[i].ring_enc[0]; uvd 938 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c for (k = 0; k < adev->uvd.num_uvd_inst; ++k) { uvd 939 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c if (adev->uvd.harvest_config & (1 << k)) uvd 952 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c for (k = 0; k < adev->uvd.num_uvd_inst; ++k) { uvd 953 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c if (adev->uvd.harvest_config & (1 << k)) uvd 955 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c ring = &adev->uvd.inst[k].ring; uvd 1093 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c ring = &adev->uvd.inst[k].ring_enc[0]; uvd 1100 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c ring = &adev->uvd.inst[k].ring_enc[1]; uvd 1121 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c for (i = 0; i < adev->uvd.num_uvd_inst; ++i) { uvd 1122 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c if (adev->uvd.harvest_config & (1 << i)) uvd 1468 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c adev->uvd.inst[ring->me].srbm_soft_reset = srbm_soft_reset; uvd 1471 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c adev->uvd.inst[ring->me].srbm_soft_reset = 0; uvd 1480 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c if (!adev->uvd.inst[ring->me].srbm_soft_reset) uvd 1492 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c if (!adev->uvd.inst[ring->me].srbm_soft_reset) uvd 1494 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c srbm_soft_reset = adev->uvd.inst[ring->me].srbm_soft_reset; uvd 1522 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c if (!adev->uvd.inst[ring->me].srbm_soft_reset) uvd 1562 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c amdgpu_fence_process(&adev->uvd.inst[ip_instance].ring); uvd 1565 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c amdgpu_fence_process(&adev->uvd.inst[ip_instance].ring_enc[0]); uvd 1569 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c amdgpu_fence_process(&adev->uvd.inst[ip_instance].ring_enc[1]); uvd 1841 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c for (i = 0; i < adev->uvd.num_uvd_inst; i++) { uvd 1842 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c if (adev->uvd.harvest_config & (1 << i)) uvd 1844 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c adev->uvd.inst[i].ring.funcs = &uvd_v7_0_ring_vm_funcs; uvd 1845 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c adev->uvd.inst[i].ring.me = i; uvd 1854 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c for (j = 0; j < adev->uvd.num_uvd_inst; j++) { uvd 1855 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c if (adev->uvd.harvest_config & (1 << j)) uvd 1857 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c for (i = 0; i < adev->uvd.num_enc_rings; ++i) { uvd 1858 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c adev->uvd.inst[j].ring_enc[i].funcs = &uvd_v7_0_enc_ring_vm_funcs; uvd 1859 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c adev->uvd.inst[j].ring_enc[i].me = j; uvd 1875 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c for (i = 0; i < adev->uvd.num_uvd_inst; i++) { uvd 1876 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c if (adev->uvd.harvest_config & (1 << i)) uvd 1878 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c adev->uvd.inst[i].irq.num_types = adev->uvd.num_enc_rings + 1; uvd 1879 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c adev->uvd.inst[i].irq.funcs = &uvd_v7_0_irq_funcs; uvd 112 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h uint32_t uvd : 1; uvd 135 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h uint32_t uvd : 1; uvd 2383 drivers/gpu/drm/radeon/radeon.h struct radeon_uvd uvd; uvd 301 drivers/gpu/drm/radeon/radeon_drv.c MODULE_PARM_DESC(uvd, "uvd enable/disable uvd support (1 = enable, 0 = disable)"); uvd 302 drivers/gpu/drm/radeon/radeon_drv.c module_param_named(uvd, radeon_uvd, int, 0444); uvd 850 drivers/gpu/drm/radeon/radeon_fence.c rdev->fence_drv[ring].cpu_addr = rdev->uvd.cpu_addr + index; uvd 851 drivers/gpu/drm/radeon/radeon_fence.c rdev->fence_drv[ring].gpu_addr = rdev->uvd.gpu_addr + index; uvd 72 drivers/gpu/drm/radeon/radeon_uvd.c INIT_DELAYED_WORK(&rdev->uvd.idle_work, radeon_uvd_idle_work_handler); uvd 137 drivers/gpu/drm/radeon/radeon_uvd.c rdev->uvd.fw_header_present = false; uvd 138 drivers/gpu/drm/radeon/radeon_uvd.c rdev->uvd.max_handles = RADEON_DEFAULT_UVD_HANDLES; uvd 153 drivers/gpu/drm/radeon/radeon_uvd.c rdev->uvd.fw_header_present = true; uvd 166 drivers/gpu/drm/radeon/radeon_uvd.c rdev->uvd.max_handles = RADEON_MAX_UVD_HANDLES; uvd 186 drivers/gpu/drm/radeon/radeon_uvd.c RADEON_UVD_SESSION_SIZE * rdev->uvd.max_handles; uvd 189 drivers/gpu/drm/radeon/radeon_uvd.c NULL, &rdev->uvd.vcpu_bo); uvd 195 drivers/gpu/drm/radeon/radeon_uvd.c r = radeon_bo_reserve(rdev->uvd.vcpu_bo, false); uvd 197 drivers/gpu/drm/radeon/radeon_uvd.c radeon_bo_unref(&rdev->uvd.vcpu_bo); uvd 202 drivers/gpu/drm/radeon/radeon_uvd.c r = radeon_bo_pin(rdev->uvd.vcpu_bo, RADEON_GEM_DOMAIN_VRAM, uvd 203 drivers/gpu/drm/radeon/radeon_uvd.c &rdev->uvd.gpu_addr); uvd 205 drivers/gpu/drm/radeon/radeon_uvd.c radeon_bo_unreserve(rdev->uvd.vcpu_bo); uvd 206 drivers/gpu/drm/radeon/radeon_uvd.c radeon_bo_unref(&rdev->uvd.vcpu_bo); uvd 211 drivers/gpu/drm/radeon/radeon_uvd.c r = radeon_bo_kmap(rdev->uvd.vcpu_bo, &rdev->uvd.cpu_addr); uvd 217 drivers/gpu/drm/radeon/radeon_uvd.c radeon_bo_unreserve(rdev->uvd.vcpu_bo); uvd 219 drivers/gpu/drm/radeon/radeon_uvd.c for (i = 0; i < rdev->uvd.max_handles; ++i) { uvd 220 drivers/gpu/drm/radeon/radeon_uvd.c atomic_set(&rdev->uvd.handles[i], 0); uvd 221 drivers/gpu/drm/radeon/radeon_uvd.c rdev->uvd.filp[i] = NULL; uvd 222 drivers/gpu/drm/radeon/radeon_uvd.c rdev->uvd.img_size[i] = 0; uvd 232 drivers/gpu/drm/radeon/radeon_uvd.c if (rdev->uvd.vcpu_bo == NULL) uvd 235 drivers/gpu/drm/radeon/radeon_uvd.c r = radeon_bo_reserve(rdev->uvd.vcpu_bo, false); uvd 237 drivers/gpu/drm/radeon/radeon_uvd.c radeon_bo_kunmap(rdev->uvd.vcpu_bo); uvd 238 drivers/gpu/drm/radeon/radeon_uvd.c radeon_bo_unpin(rdev->uvd.vcpu_bo); uvd 239 drivers/gpu/drm/radeon/radeon_uvd.c radeon_bo_unreserve(rdev->uvd.vcpu_bo); uvd 242 drivers/gpu/drm/radeon/radeon_uvd.c radeon_bo_unref(&rdev->uvd.vcpu_bo); uvd 253 drivers/gpu/drm/radeon/radeon_uvd.c if (rdev->uvd.vcpu_bo == NULL) uvd 256 drivers/gpu/drm/radeon/radeon_uvd.c for (i = 0; i < rdev->uvd.max_handles; ++i) { uvd 257 drivers/gpu/drm/radeon/radeon_uvd.c uint32_t handle = atomic_read(&rdev->uvd.handles[i]); uvd 273 drivers/gpu/drm/radeon/radeon_uvd.c rdev->uvd.filp[i] = NULL; uvd 274 drivers/gpu/drm/radeon/radeon_uvd.c atomic_set(&rdev->uvd.handles[i], 0); uvd 286 drivers/gpu/drm/radeon/radeon_uvd.c if (rdev->uvd.vcpu_bo == NULL) uvd 289 drivers/gpu/drm/radeon/radeon_uvd.c memcpy(rdev->uvd.cpu_addr, rdev->uvd_fw->data, rdev->uvd_fw->size); uvd 291 drivers/gpu/drm/radeon/radeon_uvd.c size = radeon_bo_size(rdev->uvd.vcpu_bo); uvd 294 drivers/gpu/drm/radeon/radeon_uvd.c ptr = rdev->uvd.cpu_addr; uvd 331 drivers/gpu/drm/radeon/radeon_uvd.c for (i = 0; i < rdev->uvd.max_handles; ++i) { uvd 332 drivers/gpu/drm/radeon/radeon_uvd.c uint32_t handle = atomic_read(&rdev->uvd.handles[i]); uvd 333 drivers/gpu/drm/radeon/radeon_uvd.c if (handle != 0 && rdev->uvd.filp[i] == filp) { uvd 348 drivers/gpu/drm/radeon/radeon_uvd.c rdev->uvd.filp[i] = NULL; uvd 349 drivers/gpu/drm/radeon/radeon_uvd.c atomic_set(&rdev->uvd.handles[i], 0); uvd 516 drivers/gpu/drm/radeon/radeon_uvd.c for (i = 0; i < p->rdev->uvd.max_handles; ++i) { uvd 517 drivers/gpu/drm/radeon/radeon_uvd.c if (atomic_read(&p->rdev->uvd.handles[i]) == handle) { uvd 522 drivers/gpu/drm/radeon/radeon_uvd.c if (!atomic_cmpxchg(&p->rdev->uvd.handles[i], 0, handle)) { uvd 523 drivers/gpu/drm/radeon/radeon_uvd.c p->rdev->uvd.filp[i] = p->filp; uvd 524 drivers/gpu/drm/radeon/radeon_uvd.c p->rdev->uvd.img_size[i] = img_size; uvd 542 drivers/gpu/drm/radeon/radeon_uvd.c for (i = 0; i < p->rdev->uvd.max_handles; ++i) { uvd 543 drivers/gpu/drm/radeon/radeon_uvd.c if (atomic_read(&p->rdev->uvd.handles[i]) == handle) { uvd 544 drivers/gpu/drm/radeon/radeon_uvd.c if (p->rdev->uvd.filp[i] != p->filp) { uvd 557 drivers/gpu/drm/radeon/radeon_uvd.c for (i = 0; i < p->rdev->uvd.max_handles; ++i) uvd 558 drivers/gpu/drm/radeon/radeon_uvd.c atomic_cmpxchg(&p->rdev->uvd.handles[i], handle, 0); uvd 625 drivers/gpu/drm/radeon/radeon_uvd.c (start >> 28) != (p->rdev->uvd.gpu_addr >> 28)) { uvd 781 drivers/gpu/drm/radeon/radeon_uvd.c uint64_t offs = radeon_bo_size(rdev->uvd.vcpu_bo) - uvd 784 drivers/gpu/drm/radeon/radeon_uvd.c uint32_t *msg = rdev->uvd.cpu_addr + offs; uvd 785 drivers/gpu/drm/radeon/radeon_uvd.c uint64_t addr = rdev->uvd.gpu_addr + offs; uvd 789 drivers/gpu/drm/radeon/radeon_uvd.c r = radeon_bo_reserve(rdev->uvd.vcpu_bo, true); uvd 809 drivers/gpu/drm/radeon/radeon_uvd.c radeon_bo_unreserve(rdev->uvd.vcpu_bo); uvd 817 drivers/gpu/drm/radeon/radeon_uvd.c uint64_t offs = radeon_bo_size(rdev->uvd.vcpu_bo) - uvd 820 drivers/gpu/drm/radeon/radeon_uvd.c uint32_t *msg = rdev->uvd.cpu_addr + offs; uvd 821 drivers/gpu/drm/radeon/radeon_uvd.c uint64_t addr = rdev->uvd.gpu_addr + offs; uvd 825 drivers/gpu/drm/radeon/radeon_uvd.c r = radeon_bo_reserve(rdev->uvd.vcpu_bo, true); uvd 838 drivers/gpu/drm/radeon/radeon_uvd.c radeon_bo_unreserve(rdev->uvd.vcpu_bo); uvd 859 drivers/gpu/drm/radeon/radeon_uvd.c for (i = 0; i < rdev->uvd.max_handles; ++i) { uvd 860 drivers/gpu/drm/radeon/radeon_uvd.c if (!atomic_read(&rdev->uvd.handles[i])) uvd 863 drivers/gpu/drm/radeon/radeon_uvd.c if (rdev->uvd.img_size[i] >= 720*576) uvd 873 drivers/gpu/drm/radeon/radeon_uvd.c container_of(work, struct radeon_device, uvd.idle_work.work); uvd 884 drivers/gpu/drm/radeon/radeon_uvd.c schedule_delayed_work(&rdev->uvd.idle_work, uvd 892 drivers/gpu/drm/radeon/radeon_uvd.c bool set_clocks = !cancel_delayed_work_sync(&rdev->uvd.idle_work); uvd 893 drivers/gpu/drm/radeon/radeon_uvd.c set_clocks &= schedule_delayed_work(&rdev->uvd.idle_work, uvd 121 drivers/gpu/drm/radeon/uvd_v1_0.c addr = (rdev->uvd.gpu_addr >> 3) + 16; uvd 133 drivers/gpu/drm/radeon/uvd_v1_0.c (RADEON_UVD_SESSION_SIZE * rdev->uvd.max_handles)) >> 3; uvd 138 drivers/gpu/drm/radeon/uvd_v1_0.c addr = (rdev->uvd.gpu_addr >> 28) & 0xF; uvd 142 drivers/gpu/drm/radeon/uvd_v1_0.c addr = (rdev->uvd.gpu_addr >> 32) & 0xFF; uvd 145 drivers/gpu/drm/radeon/uvd_v1_0.c WREG32(UVD_FW_START, *((uint32_t*)rdev->uvd.cpu_addr)); uvd 113 drivers/gpu/drm/radeon/uvd_v2_2.c addr = rdev->uvd.gpu_addr >> 3; uvd 125 drivers/gpu/drm/radeon/uvd_v2_2.c (RADEON_UVD_SESSION_SIZE * rdev->uvd.max_handles)) >> 3; uvd 130 drivers/gpu/drm/radeon/uvd_v2_2.c addr = (rdev->uvd.gpu_addr >> 28) & 0xF; uvd 134 drivers/gpu/drm/radeon/uvd_v2_2.c addr = (rdev->uvd.gpu_addr >> 32) & 0xFF; uvd 46 drivers/gpu/drm/radeon/uvd_v4_2.c if (rdev->uvd.fw_header_present) uvd 47 drivers/gpu/drm/radeon/uvd_v4_2.c addr = (rdev->uvd.gpu_addr + 0x200) >> 3; uvd 49 drivers/gpu/drm/radeon/uvd_v4_2.c addr = rdev->uvd.gpu_addr >> 3; uvd 62 drivers/gpu/drm/radeon/uvd_v4_2.c (RADEON_UVD_SESSION_SIZE * rdev->uvd.max_handles)) >> 3; uvd 67 drivers/gpu/drm/radeon/uvd_v4_2.c addr = (rdev->uvd.gpu_addr >> 28) & 0xF; uvd 71 drivers/gpu/drm/radeon/uvd_v4_2.c addr = (rdev->uvd.gpu_addr >> 32) & 0xFF; uvd 74 drivers/gpu/drm/radeon/uvd_v4_2.c if (rdev->uvd.fw_header_present) uvd 75 drivers/gpu/drm/radeon/uvd_v4_2.c WREG32(UVD_GP_SCRATCH4, rdev->uvd.max_handles);