UVD_BASE           42 drivers/gpu/drm/amd/amdgpu/arct_reg_init.c 		adev->reg_offset[UVD_HWIP][i] = (uint32_t *)(&(UVD_BASE.instance[i]));
UVD_BASE           42 drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c 		adev->reg_offset[UVD_HWIP][i] = (uint32_t *)(&(UVD_BASE.instance[i]));
UVD_BASE           42 drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c 		adev->reg_offset[UVD_HWIP][i] = (uint32_t *)(&(UVD_BASE.instance[i]));
UVD_BASE          219 drivers/gpu/drm/amd/include/arct_ip_offset.h static const struct IP_BASE UVD_BASE            ={ { { { 0x00007800, 0x00007E00, 0x00012180, 0x00403000, 0, 0 } },
UVD_BASE           78 drivers/gpu/drm/amd/include/vega10_ip_offset.h static const struct IP_BASE UVD_BASE			= { { { { 0x00007800, 0x00007E00, 0, 0, 0 } },
UVD_BASE          141 drivers/gpu/drm/amd/include/vega20_ip_offset.h static const struct IP_BASE UVD_BASE            ={ { { { 0x00007800, 0x00007E00, 0, 0, 0, 0 } },