UVD0_BASE          42 drivers/gpu/drm/amd/amdgpu/navi12_reg_init.c 		adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(UVD0_BASE.instance[i]));
UVD0_BASE          42 drivers/gpu/drm/amd/amdgpu/navi14_reg_init.c 		adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(UVD0_BASE.instance[i]));
UVD0_BASE         186 drivers/gpu/drm/amd/include/navi12_ip_offset.h static const struct IP_BASE UVD0_BASE ={ { { { 0x00007800, 0x00007E00, 0x02403000, 0, 0 } },
UVD0_BASE         186 drivers/gpu/drm/amd/include/navi14_ip_offset.h static const struct IP_BASE UVD0_BASE ={ { { { 0x00007800, 0x00007E00, 0x02403000, 0, 0 } },
UVD0_BASE         221 drivers/gpu/drm/amd/include/renoir_ip_offset.h static const struct IP_BASE UVD0_BASE ={ { { { 0x00007800, 0x00007E00, 0x02403000, 0, 0 } },