UVD 175 drivers/gpu/drm/amd/amdgpu/soc15.c address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX); UVD 176 drivers/gpu/drm/amd/amdgpu/soc15.c data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA); UVD 189 drivers/gpu/drm/amd/amdgpu/soc15.c address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX); UVD 190 drivers/gpu/drm/amd/amdgpu/soc15.c data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA); UVD 75 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c return RREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_RPTR); UVD 90 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c return RREG32_SOC15(UVD, ring->me, mmUVD_RB_RPTR); UVD 92 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c return RREG32_SOC15(UVD, ring->me, mmUVD_RB_RPTR2); UVD 106 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c return RREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR); UVD 124 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c return RREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR); UVD 126 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c return RREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR2); UVD 140 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); UVD 162 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR, UVD 165 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR2, UVD 379 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c harvest = RREG32_SOC15(UVD, i, mmUVD_PG0_CC_UVD_HARVESTING); UVD 550 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c tmp = PACKET0(SOC15_REG_OFFSET(UVD, j, UVD 555 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c tmp = PACKET0(SOC15_REG_OFFSET(UVD, j, UVD 560 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c tmp = PACKET0(SOC15_REG_OFFSET(UVD, j, UVD 566 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, j, UVD 570 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, j, UVD 660 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, UVD 664 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, UVD 668 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET0, 0); UVD 671 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, UVD 673 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, UVD 676 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET0, UVD 680 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE0, size); UVD 682 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, UVD 684 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, UVD 686 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET1, (1 << 21)); UVD 687 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_UVD_HEAP_SIZE); UVD 689 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, UVD 691 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, UVD 693 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET2, (2 << 21)); UVD 694 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE2, UVD 697 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, i, mmUVD_UDEC_ADDR_CONFIG, UVD 699 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, i, mmUVD_UDEC_DB_ADDR_CONFIG, UVD 701 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, i, mmUVD_UDEC_DBW_ADDR_CONFIG, UVD 704 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, i, mmUVD_GP_SCRATCH4, adev->uvd.max_handles); UVD 800 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS), UVD 804 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, UVD 807 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, UVD 810 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0); UVD 813 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), UVD 815 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), UVD 818 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), UVD 823 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE0), size); UVD 825 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), UVD 827 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), UVD 829 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET1), (1 << 21)); UVD 830 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_UVD_HEAP_SIZE); UVD 832 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), UVD 834 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), UVD 836 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET2), (2 << 21)); UVD 837 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE2), UVD 840 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_GP_SCRATCH4), adev->uvd.max_handles); UVD 844 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_CGC_CTRL), UVD 848 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_MASTINT_EN), UVD 852 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2), UVD 857 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET), UVD 868 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL), UVD 877 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET), UVD 881 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL), UVD 885 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_MASTINT_EN), UVD 890 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS), UVD 897 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RBC_RB_CNTL), tmp); UVD 901 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_LO), ring->gpu_addr); UVD 902 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_HI), upper_32_bits(ring->gpu_addr)); UVD 903 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_SIZE), ring->ring_size / 4); UVD 906 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET), 0); UVD 909 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2), UVD 912 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c MMSCH_V1_0_INSERT_DIRECT_POLL(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS), 0x02, 0x02); UVD 942 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_POWER_STATUS), 0, UVD 957 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_CGC_CTRL), 0, UVD 961 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_MASTINT_EN), 0, UVD 965 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_LMI_CTRL2), UVD 971 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, k, mmUVD_SOFT_RESET, UVD 983 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, k, mmUVD_LMI_CTRL, UVD 996 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, k, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); UVD 997 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, k, mmUVD_MP_SWAP_CNTL, mp_swap_cntl); UVD 999 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXA0, 0x40c2040); UVD 1000 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXA1, 0x0); UVD 1001 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXB0, 0x40c2040); UVD 1002 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXB1, 0x0); UVD 1003 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, k, mmUVD_MPC_SET_ALU, 0); UVD 1004 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUX, 0x88); UVD 1007 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, k, mmUVD_SOFT_RESET, UVD 1012 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, k, mmUVD_VCPU_CNTL, UVD 1016 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_LMI_CTRL2), 0, UVD 1020 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, k, mmUVD_SOFT_RESET, 0); UVD 1027 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c status = RREG32_SOC15(UVD, k, mmUVD_STATUS); UVD 1037 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_SOFT_RESET), UVD 1041 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_SOFT_RESET), 0, UVD 1052 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_MASTINT_EN), UVD 1057 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_STATUS), 0, UVD 1068 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, k, mmUVD_RBC_RB_CNTL, tmp); UVD 1071 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, k, mmUVD_RBC_RB_WPTR_CNTL, 0); UVD 1074 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, k, mmUVD_RBC_RB_RPTR_ADDR, UVD 1078 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, k, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, UVD 1080 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, k, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, UVD 1084 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, k, mmUVD_RBC_RB_RPTR, 0); UVD 1086 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c ring->wptr = RREG32_SOC15(UVD, k, mmUVD_RBC_RB_RPTR); UVD 1087 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, k, mmUVD_RBC_RB_WPTR, UVD 1090 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_RBC_RB_CNTL), 0, UVD 1094 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, k, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); UVD 1095 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, k, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); UVD 1096 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, k, mmUVD_RB_BASE_LO, ring->gpu_addr); UVD 1097 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, k, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); UVD 1098 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, k, mmUVD_RB_SIZE, ring->ring_size / 4); UVD 1101 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, k, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); UVD 1102 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, k, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); UVD 1103 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, k, mmUVD_RB_BASE_LO2, ring->gpu_addr); UVD 1104 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, k, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); UVD 1105 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, k, mmUVD_RB_SIZE2, ring->ring_size / 4); UVD 1125 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, i, mmUVD_RBC_RB_CNTL, 0x11010101); UVD 1128 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2), UVD 1134 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, i, mmUVD_SOFT_RESET, UVD 1139 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, i, mmUVD_VCPU_CNTL, 0x0); UVD 1142 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2), 0, UVD 1163 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_CONTEXT_ID), 0)); UVD 1166 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0)); UVD 1169 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0)); UVD 1172 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0)); UVD 1176 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0)); UVD 1179 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0)); UVD 1182 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0)); UVD 1231 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, ring->me, mmUVD_CONTEXT_ID, 0xCAFEDEAD); UVD 1237 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_CONTEXT_ID), 0)); UVD 1241 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c tmp = RREG32_SOC15(UVD, ring->me, mmUVD_CONTEXT_ID); UVD 1299 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_VMID), 0)); UVD 1303 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_64BIT_BAR_LOW), 0)); UVD 1306 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH), 0)); UVD 1309 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_RBC_IB_SIZE), 0)); UVD 1341 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0)); UVD 1344 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0)); UVD 1347 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0)); UVD 1357 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0)); UVD 1360 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0)); UVD 1363 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GP_SCRATCH8), 0)); UVD 1366 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0)); UVD 1393 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_NO_OP), 0)); UVD 1462 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c (RREG32_SOC15(UVD, ring->me, mmUVD_STATUS) & UVD 1585 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c data = RREG32_SOC15(UVD, ring->me, mmUVD_CGC_CTRL); UVD 1586 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c data1 = RREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE); UVD 1587 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c data2 = RREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_CTRL); UVD 1631 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, ring->me, mmUVD_CGC_CTRL, data); UVD 1632 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, ring->me, mmUVD_CGC_GATE, 0); UVD 1633 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE, data1); UVD 1634 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_CTRL, data2); UVD 1641 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c data = RREG32_SOC15(UVD, ring->me, mmUVD_CGC_GATE); UVD 1642 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c data1 = RREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE); UVD 1674 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, ring->me, mmUVD_CGC_GATE, data); UVD 1675 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE, data1); UVD 1734 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, ring->me, mmUVD_POWER_STATUS, UVD_POWER_STATUS__UVD_PG_EN_MASK); UVD 134 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9); UVD 136 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0); UVD 138 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1); UVD 140 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD); UVD 142 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP); UVD 160 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_PITCH); UVD 301 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, UVD 303 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, UVD 305 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0); UVD 308 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, UVD 310 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, UVD 313 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, UVD 317 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size); UVD 320 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, UVD 322 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, UVD 324 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0); UVD 325 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); UVD 328 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, UVD 330 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, UVD 332 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0); UVD 333 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); UVD 335 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_UDEC_ADDR_CONFIG, UVD 337 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_UDEC_DB_ADDR_CONFIG, UVD 339 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG, UVD 341 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_UDEC_DBW_UV_ADDR_CONFIG, UVD 343 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_MIF_CURR_ADDR_CONFIG, UVD 345 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_MIF_CURR_UV_ADDR_CONFIG, UVD 347 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_MIF_RECON1_ADDR_CONFIG, UVD 349 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_MIF_RECON1_UV_ADDR_CONFIG, UVD 351 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_MIF_REF_ADDR_CONFIG, UVD 353 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_MIF_REF_UV_ADDR_CONFIG, UVD 355 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_JPEG_ADDR_CONFIG, UVD 357 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_JPEG_UV_ADDR_CONFIG, UVD 368 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, UVD 371 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, UVD 374 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0, UVD 378 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, UVD 380 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, UVD 383 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, UVD 387 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size, 0xFFFFFFFF, 0); UVD 390 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, UVD 392 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, UVD 394 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0, UVD 396 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE, UVD 400 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, UVD 403 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, UVD 406 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0, 0xFFFFFFFF, 0); UVD 407 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE, UVD 411 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_UDEC_ADDR_CONFIG, UVD 413 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_UDEC_DB_ADDR_CONFIG, UVD 415 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG, UVD 417 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_UDEC_DBW_UV_ADDR_CONFIG, UVD 419 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MIF_CURR_ADDR_CONFIG, UVD 421 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MIF_CURR_UV_ADDR_CONFIG, UVD 423 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MIF_RECON1_ADDR_CONFIG, UVD 425 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MIF_RECON1_UV_ADDR_CONFIG, UVD 427 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MIF_REF_ADDR_CONFIG, UVD 429 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MIF_REF_UV_ADDR_CONFIG, UVD 644 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmJPEG_CGC_CTRL, reg_data, 0xFFFFFFFF, sram_sel); UVD 646 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmJPEG_CGC_GATE, 0, 0xFFFFFFFF, sram_sel); UVD 675 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_CGC_CTRL, reg_data, 0xFFFFFFFF, sram_sel); UVD 678 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_CGC_GATE, 0, 0xFFFFFFFF, sram_sel); UVD 681 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SUVD_CGC_GATE, 1, 0xFFFFFFFF, sram_sel); UVD 684 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SUVD_CGC_CTRL, 0, 0xFFFFFFFF, sram_sel); UVD 794 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY; UVD 795 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp); UVD 801 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0, UVD 805 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c tmp = RREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL); UVD 806 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL, tmp | UVD 816 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); UVD 818 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c tmp = RREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL); UVD 821 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL, tmp); UVD 823 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA0, UVD 829 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB0, UVD 835 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUX, UVD 842 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_REG_XX_MASK, 0x10); UVD 843 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK, UVD 844 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c RREG32_SOC15(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK) | 0x3); UVD 847 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_VCPU_CNTL, UVD_VCPU_CNTL__CLK_EN_MASK); UVD 850 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0, UVD 854 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0, UVD 857 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c tmp = RREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET); UVD 860 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET, tmp); UVD 866 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c status = RREG32_SOC15(UVD, 0, mmUVD_STATUS); UVD 876 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), UVD 880 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0, UVD 891 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), UVD 895 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SYS_INT_EN), UVD 900 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) & ~UVD_STATUS__UVD_BUSY; UVD 901 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp); UVD 910 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp); UVD 913 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0); UVD 916 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR, UVD 920 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, UVD 922 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, UVD 926 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0); UVD 928 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 0); UVD 930 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); UVD 931 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, UVD 934 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0, UVD 938 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); UVD 939 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); UVD 940 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr); UVD 941 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); UVD 942 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4); UVD 945 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); UVD 946 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); UVD 947 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr); UVD 948 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); UVD 949 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4); UVD 952 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_VMID, 0); UVD 953 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK | UVD 955 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW, lower_32_bits(ring->gpu_addr)); UVD 956 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, upper_32_bits(ring->gpu_addr)); UVD 957 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR, 0); UVD 958 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, 0); UVD 959 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK); UVD 962 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR); UVD 983 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c tmp = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS); UVD 986 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, tmp); UVD 995 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CNTL, tmp, 0xFFFFFFFF, 0); UVD 998 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MASTINT_EN, UVD 1002 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL, UVD 1016 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl, 0xFFFFFFFF, 0); UVD 1018 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_CNTL, UVD 1021 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUXA0, UVD 1027 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUXB0, UVD 1033 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUX, UVD 1040 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_REG_XX_MASK, 0x10, 0xFFFFFFFF, 0); UVD 1041 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK, 0x3, 0xFFFFFFFF, 0); UVD 1044 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SOFT_RESET, 0, 0xFFFFFFFF, 0); UVD 1047 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL2, UVD 1052 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MASTINT_EN, UVD 1057 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL, UVD 1069 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_JPEG_ADDR_CONFIG, tmp, 0xFFFFFFFF, 1); UVD 1070 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_JPEG_UV_ADDR_CONFIG, tmp, 0xFFFFFFFF, 1); UVD 1073 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SYS_INT_EN, UVD 1083 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp); UVD 1086 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0); UVD 1089 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR, UVD 1093 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, UVD 1095 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, UVD 1099 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0); UVD 1101 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 0); UVD 1103 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); UVD 1104 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, UVD 1107 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0, UVD 1112 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR); UVD 1143 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7, ret_code); UVD 1149 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_LMI_STATUS, tmp, tmp, ret_code); UVD 1152 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), UVD 1158 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_LMI_STATUS, tmp, tmp, ret_code); UVD 1161 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0, UVD 1165 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), UVD 1169 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), UVD 1173 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_STATUS, 0); UVD 1186 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, UVD 1191 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR); UVD 1192 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF, ret_code); UVD 1194 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2); UVD 1195 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF, ret_code); UVD 1197 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c tmp = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR); UVD 1198 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_JRBC_RB_RPTR, tmp, 0xFFFFFFFF, ret_code); UVD 1200 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c tmp = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF; UVD 1201 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF, ret_code); UVD 1203 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, UVD 1208 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0, UVD 1240 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) & UVD 1247 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, UVD 1254 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); UVD 1255 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE, UVD 1261 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr); UVD 1262 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); UVD 1263 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4); UVD 1264 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); UVD 1265 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); UVD 1268 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr); UVD 1269 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); UVD 1270 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4); UVD 1271 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); UVD 1272 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); UVD 1275 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, UVD 1276 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF); UVD 1277 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, UVD 1284 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); UVD 1295 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) & UVD 1302 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, UVD 1308 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c reg_data2 = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS); UVD 1310 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, reg_data2); UVD 1314 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); UVD 1315 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE, UVD 1321 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_VMID, 0); UVD 1322 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, UVD 1325 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW, UVD 1327 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, UVD 1329 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR, ring->wptr); UVD 1330 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, ring->wptr); UVD 1331 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, UVD 1335 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, UVD 1336 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF); UVD 1337 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, UVD 1344 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); UVD 1399 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); UVD 1413 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR); UVD 1428 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, UVD 1431 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); UVD 1446 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); UVD 1449 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); UVD 1465 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); UVD 1485 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0)); UVD 1488 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); UVD 1491 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0)); UVD 1494 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); UVD 1498 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); UVD 1501 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0)); UVD 1504 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); UVD 1525 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_VMID), 0)); UVD 1529 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_LOW), 0)); UVD 1532 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH), 0)); UVD 1535 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_IB_SIZE), 0)); UVD 1546 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); UVD 1549 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0)); UVD 1552 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GP_SCRATCH8), 0)); UVD 1555 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); UVD 1580 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); UVD 1583 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0)); UVD 1586 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); UVD 1602 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR); UVD 1604 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2); UVD 1619 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR); UVD 1621 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2); UVD 1636 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, UVD 1639 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, UVD 1732 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c return RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR); UVD 1746 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c return RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR); UVD 1760 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr)); UVD 1775 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0)); UVD 1794 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0)); UVD 1817 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_GPCOM_DATA0), 0, 0, PACKETJ_TYPE0)); UVD 1821 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_GPCOM_DATA1), 0, 0, PACKETJ_TYPE0)); UVD 1825 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW), 0, 0, PACKETJ_TYPE0)); UVD 1829 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0)); UVD 1833 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_GPCOM_CMD), 0, 0, PACKETJ_TYPE0)); UVD 1837 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_GPCOM_CMD), 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE4)); UVD 1841 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_TYPE0)); UVD 1845 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0)); UVD 1849 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW), 0, 0, PACKETJ_TYPE0)); UVD 1853 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0)); UVD 1861 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0)); UVD 1890 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_IB_VMID), 0, 0, PACKETJ_TYPE0)); UVD 1894 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JPEG_VMID), 0, 0, PACKETJ_TYPE0)); UVD 1898 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW), 0, 0, PACKETJ_TYPE0)); UVD 1902 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0)); UVD 1906 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_IB_SIZE), 0, 0, PACKETJ_TYPE0)); UVD 1910 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW), 0, 0, PACKETJ_TYPE0)); UVD 1914 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0)); UVD 1922 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_TYPE0)); UVD 1926 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0)); UVD 1930 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_STATUS), 0, PACKETJ_CONDITION_CHECK3, PACKETJ_TYPE3)); UVD 1942 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_TYPE0)); UVD 1946 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0)); UVD 1950 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0)); UVD 1986 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0)); UVD 2015 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c ring->ring[(*ptr)++] = PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0); UVD 2034 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW); UVD 2040 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH); UVD 2052 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_CNTL); UVD 2058 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_REF_DATA); UVD 2064 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_CNTL); UVD 2069 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c ring->ring[ptr++] = PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_TYPE0); UVD 2071 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c ring->ring[ptr++] = PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0); UVD 2073 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c ring->ring[ptr++] = PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0); UVD 2091 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_RPTR); UVD 2097 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_CNTL); UVD 2147 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP), 0)); UVD 177 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c adev->vcn.inst->external.scratch9 = SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9); UVD 179 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c adev->vcn.inst->external.data0 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0); UVD 181 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c adev->vcn.inst->external.data1 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1); UVD 183 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c adev->vcn.inst->external.cmd = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD); UVD 185 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c adev->vcn.inst->external.nop = SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP); UVD 208 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c adev->vcn.inst->external.jpeg_pitch = SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_PITCH); UVD 370 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, UVD 372 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, UVD 374 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0); UVD 377 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, UVD 379 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, UVD 382 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, UVD 386 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size); UVD 389 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, UVD 391 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, UVD 393 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0); UVD 394 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); UVD 397 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, UVD 399 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, UVD 401 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0); UVD 402 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); UVD 404 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_SOC15(UVD, 0, mmUVD_GFX10_ADDR_CONFIG, adev->gfx.config.gb_addr_config); UVD 405 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_SOC15(UVD, 0, mmJPEG_DEC_GFX10_ADDR_CONFIG, adev->gfx.config.gb_addr_config); UVD 417 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), UVD 420 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), UVD 423 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); UVD 426 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); UVD 428 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); UVD 430 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); UVD 435 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), UVD 438 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), UVD 442 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), UVD 448 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c UVD, 0, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect); UVD 451 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c UVD, 0, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); UVD 456 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), UVD 459 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), UVD 462 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); UVD 465 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect); UVD 467 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect); UVD 469 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); UVD 472 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c UVD, 0, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); UVD 476 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), UVD 479 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), UVD 482 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c UVD, 0, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect); UVD 484 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c UVD, 0, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); UVD 488 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 0, 0, indirect); UVD 490 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 0, 0, indirect); UVD 492 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c UVD, 0, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect); UVD 494 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c UVD, 0, mmUVD_VCPU_NONCACHE_SIZE0), 0, 0, indirect); UVD 498 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c UVD, 0, mmUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); UVD 644 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c UVD, 0, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect); UVD 648 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c UVD, 0, mmUVD_CGC_GATE), 0, sram_sel, indirect); UVD 652 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c UVD, 0, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect); UVD 656 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c UVD, 0, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect); UVD 674 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_PGFSM_CONFIG), tmp); UVD 686 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c tmp = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_POWER_STATUS)) & ~0x1; UVD 687 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_POWER_STATUS), tmp); UVD 705 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_JMI_CNTL), 0, UVD 713 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_VMID, 0); UVD 714 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L)); UVD 715 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW, UVD 717 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, UVD 719 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR, 0); UVD 720 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, 0); UVD 721 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, 0x00000002L); UVD 722 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_SIZE, ring->ring_size / 4); UVD 723 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR); UVD 741 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_JMI_CNTL), UVD 762 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c tmp = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_POWER_STATUS)); UVD 765 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_POWER_STATUS), tmp); UVD 768 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_PGFSM_CONFIG), tmp); UVD 936 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c tmp = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS); UVD 939 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, tmp); UVD 952 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c UVD, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect); UVD 956 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c UVD, 0, mmUVD_MASTINT_EN), 0, 0, indirect); UVD 968 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c UVD, 0, mmUVD_LMI_CTRL), tmp, 0, indirect); UVD 971 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c UVD, 0, mmUVD_MPC_CNTL), UVD 975 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c UVD, 0, mmUVD_MPC_SET_MUXA0), UVD 982 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c UVD, 0, mmUVD_MPC_SET_MUXB0), UVD 989 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c UVD, 0, mmUVD_MPC_SET_MUX), UVD 997 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c UVD, 0, mmUVD_REG_XX_MASK), 0x10, 0, indirect); UVD 999 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect); UVD 1003 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c UVD, 0, mmUVD_SOFT_RESET), 0, 0, indirect); UVD 1007 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c UVD, 0, mmUVD_LMI_CTRL2), UVD 1012 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c UVD, 0, mmUVD_MASTINT_EN), UVD 1027 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp); UVD 1030 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0); UVD 1033 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR, UVD 1037 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, UVD 1039 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, UVD 1043 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0); UVD 1045 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 0); UVD 1047 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); UVD 1048 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, UVD 1074 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY; UVD 1075 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp); UVD 1081 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), UVD 1085 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0, UVD 1089 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c tmp = RREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL); UVD 1090 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL, tmp | UVD 1097 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c tmp = RREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL); UVD 1103 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA0, UVD 1110 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB0, UVD 1117 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUX, UVD 1125 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0, UVD 1129 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0, UVD 1143 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_SOC15(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); UVD 1149 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c status = RREG32_SOC15(UVD, 0, mmUVD_STATUS); UVD 1159 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), UVD 1163 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0, UVD 1175 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), UVD 1180 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS), 0, UVD 1183 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_VMID, 0); UVD 1192 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp); UVD 1195 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, UVD 1197 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, UVD 1201 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0); UVD 1203 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); UVD 1204 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, UVD 1208 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); UVD 1209 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); UVD 1210 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr); UVD 1211 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); UVD 1212 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4); UVD 1215 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); UVD 1216 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); UVD 1217 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr); UVD 1218 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); UVD 1219 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4); UVD 1233 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1, UVD 1237 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR); UVD 1238 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF, ret_code); UVD 1240 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2); UVD 1241 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF, ret_code); UVD 1243 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c tmp = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR); UVD 1244 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_JRBC_RB_RPTR, tmp, 0xFFFFFFFF, ret_code); UVD 1246 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c tmp = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF; UVD 1247 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF, ret_code); UVD 1249 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1, UVD 1253 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0, UVD 1300 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0, UVD 1304 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), UVD 1309 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), UVD 1314 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), UVD 1342 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) & UVD 1347 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 0x1, UVD 1353 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); UVD 1356 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE, UVD 1362 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr); UVD 1363 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); UVD 1364 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4); UVD 1365 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); UVD 1366 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); UVD 1369 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr); UVD 1370 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); UVD 1371 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4); UVD 1372 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); UVD 1373 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); UVD 1375 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, UVD 1376 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF); UVD 1378 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, UVD 1385 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); UVD 1440 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); UVD 1457 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR); UVD 1472 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, UVD 1479 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); UVD 1661 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR); UVD 1663 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2); UVD 1681 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR); UVD 1686 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2); UVD 1706 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); UVD 1713 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); UVD 1804 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c return RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR); UVD 1821 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c return RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR); UVD 1839 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr)); UVD 81 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c harvest = RREG32_SOC15(UVD, i, mmCC_UVD_HARVESTING); UVD 176 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c adev->vcn.inst[j].external.scratch9 = SOC15_REG_OFFSET(UVD, j, mmUVD_SCRATCH9); UVD 178 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c adev->vcn.inst[j].external.data0 = SOC15_REG_OFFSET(UVD, j, mmUVD_GPCOM_VCPU_DATA0); UVD 180 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c adev->vcn.inst[j].external.data1 = SOC15_REG_OFFSET(UVD, j, mmUVD_GPCOM_VCPU_DATA1); UVD 182 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c adev->vcn.inst[j].external.cmd = SOC15_REG_OFFSET(UVD, j, mmUVD_GPCOM_VCPU_CMD); UVD 184 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c adev->vcn.inst[j].external.nop = SOC15_REG_OFFSET(UVD, j, mmUVD_NO_OP); UVD 187 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c adev->vcn.inst[j].external.jpeg_pitch = SOC15_REG_OFFSET(UVD, j, mmUVD_JPEG_PITCH); UVD 387 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, UVD 389 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, UVD 391 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET0, 0); UVD 394 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, UVD 396 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, UVD 399 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET0, UVD 402 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE0, size); UVD 405 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, UVD 407 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, UVD 409 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET1, 0); UVD 410 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); UVD 413 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, UVD 415 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, UVD 417 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET2, 0); UVD 418 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); UVD 620 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_JPEG_POWER_STATUS), 0, UVD 645 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_SOC15(UVD, i, mmJPEG_DEC_GFX8_ADDR_CONFIG, UVD 647 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_SOC15(UVD, i, mmJPEG_DEC_GFX10_ADDR_CONFIG, UVD 651 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_JMI_CNTL), 0, UVD 659 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_SOC15(UVD, i, mmUVD_LMI_JRBC_RB_VMID, 0); UVD 660 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_SOC15(UVD, i, mmUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L)); UVD 661 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_SOC15(UVD, i, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW, UVD 663 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_SOC15(UVD, i, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, UVD 665 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_SOC15(UVD, i, mmUVD_JRBC_RB_RPTR, 0); UVD 666 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_SOC15(UVD, i, mmUVD_JRBC_RB_WPTR, 0); UVD 667 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_SOC15(UVD, i, mmUVD_JRBC_RB_CNTL, 0x00000002L); UVD 668 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_SOC15(UVD, i, mmUVD_JRBC_RB_SIZE, ring->ring_size / 4); UVD 669 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c ring->wptr = RREG32_SOC15(UVD, i, mmUVD_JRBC_RB_WPTR); UVD 691 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_JMI_CNTL), UVD 703 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_JPEG_POWER_STATUS), UVD 721 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_POWER_STATUS), 0, UVD 725 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c tmp = RREG32_SOC15(UVD, i, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY; UVD 726 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_SOC15(UVD, i, mmUVD_STATUS, tmp); UVD 736 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL), UVD 740 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_MASTINT_EN), 0, UVD 744 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c tmp = RREG32_SOC15(UVD, i, mmUVD_LMI_CTRL); UVD 746 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_SOC15(UVD, i, mmUVD_LMI_CTRL, tmp | 0x8| UVD 753 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c tmp = RREG32_SOC15(UVD, i, mmUVD_MPC_CNTL); UVD 759 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_SOC15(UVD, i, mmUVD_MPC_SET_MUXA0, UVD 766 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_SOC15(UVD, i, mmUVD_MPC_SET_MUXB0, UVD 773 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_SOC15(UVD, i, mmUVD_MPC_SET_MUX, UVD 785 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_SOC15(UVD, i, mmUVD_GFX8_ADDR_CONFIG, UVD 787 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_SOC15(UVD, i, mmUVD_GFX8_ADDR_CONFIG, UVD 791 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2), 0, UVD 795 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_ARB_CTRL), 0, UVD 798 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL), 0, UVD 805 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c status = RREG32_SOC15(UVD, i, mmUVD_STATUS); UVD 818 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL), UVD 822 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL), 0, UVD 835 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_MASTINT_EN), UVD 840 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS), 0, UVD 843 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_SOC15(UVD, i, mmUVD_LMI_RBC_RB_VMID, 0); UVD 853 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_SOC15(UVD, i, mmUVD_RBC_RB_CNTL, tmp); UVD 856 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_SOC15(UVD, i, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, UVD 858 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_SOC15(UVD, i, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, UVD 862 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_SOC15(UVD, i, mmUVD_RBC_RB_RPTR, 0); UVD 864 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c ring->wptr = RREG32_SOC15(UVD, i, mmUVD_RBC_RB_RPTR); UVD 865 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_SOC15(UVD, i, mmUVD_RBC_RB_WPTR, UVD 868 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_SOC15(UVD, i, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); UVD 869 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_SOC15(UVD, i, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); UVD 870 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_SOC15(UVD, i, mmUVD_RB_BASE_LO, ring->gpu_addr); UVD 871 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_SOC15(UVD, i, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); UVD 872 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_SOC15(UVD, i, mmUVD_RB_SIZE, ring->ring_size / 4); UVD 875 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_SOC15(UVD, i, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); UVD 876 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_SOC15(UVD, i, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); UVD 877 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_SOC15(UVD, i, mmUVD_RB_BASE_LO2, ring->gpu_addr); UVD 878 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_SOC15(UVD, i, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); UVD 879 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_SOC15(UVD, i, mmUVD_RB_SIZE2, ring->ring_size / 4); UVD 923 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_ARB_CTRL), UVD 928 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL), UVD 933 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL), 0, UVD 942 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_POWER_STATUS), UVD 961 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c return RREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_RPTR); UVD 978 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c return RREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR); UVD 996 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); UVD 1042 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c return RREG32_SOC15(UVD, ring->me, mmUVD_RB_RPTR); UVD 1044 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c return RREG32_SOC15(UVD, ring->me, mmUVD_RB_RPTR2); UVD 1062 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c return RREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR); UVD 1067 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c return RREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR2); UVD 1087 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); UVD 1094 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); UVD 1140 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c return RREG32_SOC15(UVD, ring->me, mmUVD_JRBC_RB_RPTR); UVD 1157 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c return RREG32_SOC15(UVD, ring->me, mmUVD_JRBC_RB_WPTR); UVD 1175 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_SOC15(UVD, ring->me, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));