CM_SHAPER_LUT_WRITE_EN_MASK  974 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	type CM_SHAPER_LUT_WRITE_EN_MASK; \
CM_SHAPER_LUT_WRITE_EN_MASK 1235 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	uint32_t CM_SHAPER_LUT_WRITE_EN_MASK; \
CM_SHAPER_LUT_WRITE_EN_MASK  102 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_SHAPER_LUT_WRITE_EN_MASK, CM, id), \
CM_SHAPER_LUT_WRITE_EN_MASK  522 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	TF_SF(CM0_CM_SHAPER_LUT_WRITE_EN_MASK, CM_SHAPER_LUT_WRITE_EN_MASK, mask_sh), \
CM_SHAPER_LUT_WRITE_EN_MASK  388 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	REG_GET(CM_SHAPER_LUT_WRITE_EN_MASK,
CM_SHAPER_LUT_WRITE_EN_MASK  414 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	REG_UPDATE(CM_SHAPER_LUT_WRITE_EN_MASK,
CM_SHAPER_LUT_WRITE_EN_MASK  415 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 			CM_SHAPER_LUT_WRITE_EN_MASK, 7);
CM_SHAPER_LUT_WRITE_EN_MASK  416 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	REG_UPDATE(CM_SHAPER_LUT_WRITE_EN_MASK,