usVddcPhaseShedLimitsTableOffset  392 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c 		if (power_info->pplib4.usVddcPhaseShedLimitsTableOffset) {
usVddcPhaseShedLimitsTableOffset  396 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c 				 le16_to_cpu(power_info->pplib4.usVddcPhaseShedLimitsTableOffset));
usVddcPhaseShedLimitsTableOffset  232 drivers/gpu/drm/amd/include/pptable.h     USHORT                     usVddcPhaseShedLimitsTableOffset;    // Points to ATOM_PPLIB_PhaseSheddingLimits_Table
usVddcPhaseShedLimitsTableOffset 1537 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 		if (0 != powerplay_table4->usVddcPhaseShedLimitsTableOffset) {
usVddcPhaseShedLimitsTableOffset 1541 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 				le16_to_cpu(powerplay_table4->usVddcPhaseShedLimitsTableOffset));
usVddcPhaseShedLimitsTableOffset  205 drivers/gpu/drm/radeon/pptable.h     USHORT                     usVddcPhaseShedLimitsTableOffset;    // Points to ATOM_PPLIB_PhaseSheddingLimits_Table
usVddcPhaseShedLimitsTableOffset  985 drivers/gpu/drm/radeon/r600_dpm.c 		if (power_info->pplib4.usVddcPhaseShedLimitsTableOffset) {
usVddcPhaseShedLimitsTableOffset  989 drivers/gpu/drm/radeon/r600_dpm.c 				 le16_to_cpu(power_info->pplib4.usVddcPhaseShedLimitsTableOffset));