upper_pipe         58 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c 	u32 upper_pipe = 0;
upper_pipe         74 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c 			upper_pipe = lower_pipe;
upper_pipe         78 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c 				upper_pipe = FLD_INTF_2_SW_TRG_MUX;
upper_pipe         81 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c 				upper_pipe = FLD_INTF_1_SW_TRG_MUX;
upper_pipe         88 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c 	DPU_REG_WRITE(c, SPLIT_DISPLAY_UPPER_PIPE_CTRL, upper_pipe);