up_irq_info       324 drivers/gpu/drm/i915/gvt/interrupt.c 	struct intel_gvt_irq_info *up_irq_info = NULL;
up_irq_info       340 drivers/gpu/drm/i915/gvt/interrupt.c 		if (!up_irq_info)
up_irq_info       341 drivers/gpu/drm/i915/gvt/interrupt.c 			up_irq_info = irq->info[map->up_irq_group];
up_irq_info       343 drivers/gpu/drm/i915/gvt/interrupt.c 			WARN_ON(up_irq_info != irq->info[map->up_irq_group]);
up_irq_info       353 drivers/gpu/drm/i915/gvt/interrupt.c 	if (WARN_ON(!up_irq_info))
up_irq_info       356 drivers/gpu/drm/i915/gvt/interrupt.c 	if (up_irq_info->group == INTEL_GVT_IRQ_INFO_MASTER) {
up_irq_info       357 drivers/gpu/drm/i915/gvt/interrupt.c 		u32 isr = i915_mmio_reg_offset(up_irq_info->reg_base);
up_irq_info       363 drivers/gpu/drm/i915/gvt/interrupt.c 			i915_mmio_reg_offset(up_irq_info->reg_base));
up_irq_info       365 drivers/gpu/drm/i915/gvt/interrupt.c 			i915_mmio_reg_offset(up_irq_info->reg_base));
up_irq_info       370 drivers/gpu/drm/i915/gvt/interrupt.c 	if (up_irq_info->has_upstream_irq)
up_irq_info       371 drivers/gpu/drm/i915/gvt/interrupt.c 		update_upstream_irq(vgpu, up_irq_info);