up_hyst_offset   2774 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	uint32_t offset, up_hyst_offset, down_hyst_offset, clk_activity_offset, tmp;
up_hyst_offset   2801 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 				up_hyst_offset = array + (sizeof(SMU7_Discrete_GraphicsLevel) * i)
up_hyst_offset   2805 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 				offset = up_hyst_offset & ~0x3;
up_hyst_offset   2807 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 				tmp = phm_set_field_to_u32(up_hyst_offset, tmp, levels[i].UpH, sizeof(uint8_t));
up_hyst_offset   2836 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 				up_hyst_offset = mclk_array + (sizeof(SMU7_Discrete_MemoryLevel) * i)
up_hyst_offset   2840 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 				offset = up_hyst_offset & ~0x3;
up_hyst_offset   2842 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 				tmp = phm_set_field_to_u32(up_hyst_offset, tmp, mclk_levels[i].UpH, sizeof(uint8_t));
up_hyst_offset   2566 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	uint32_t offset, up_hyst_offset, down_hyst_offset, clk_activity_offset, tmp;
up_hyst_offset   2593 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 				up_hyst_offset = array + (sizeof(SMU73_Discrete_GraphicsLevel) * i)
up_hyst_offset   2597 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 				offset = up_hyst_offset & ~0x3;
up_hyst_offset   2599 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 				tmp = phm_set_field_to_u32(up_hyst_offset, tmp, levels[i].UpHyst, sizeof(uint8_t));
up_hyst_offset   2628 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 				up_hyst_offset = mclk_array + (sizeof(SMU73_Discrete_MemoryLevel) * i)
up_hyst_offset   2632 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 				offset = up_hyst_offset & ~0x3;
up_hyst_offset   2634 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 				tmp = phm_set_field_to_u32(up_hyst_offset, tmp, mclk_levels[i].UpHyst, sizeof(uint8_t));
up_hyst_offset   2479 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	uint32_t offset, up_hyst_offset, down_hyst_offset, clk_activity_offset, tmp;
up_hyst_offset   2506 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 				up_hyst_offset = array + (sizeof(SMU74_Discrete_GraphicsLevel) * i)
up_hyst_offset   2510 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 				offset = up_hyst_offset & ~0x3;
up_hyst_offset   2512 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 				tmp = phm_set_field_to_u32(up_hyst_offset, tmp, levels[i].UpHyst, sizeof(uint8_t));
up_hyst_offset   2541 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 				up_hyst_offset = mclk_array + (sizeof(SMU74_Discrete_MemoryLevel) * i)
up_hyst_offset   2545 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 				offset = up_hyst_offset & ~0x3;
up_hyst_offset   2547 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 				tmp = phm_set_field_to_u32(up_hyst_offset, tmp, mclk_levels[i].UpHyst, sizeof(uint8_t));
up_hyst_offset   3162 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	uint32_t offset, up_hyst_offset, down_hyst_offset, clk_activity_offset, tmp;
up_hyst_offset   3189 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 				up_hyst_offset = array + (sizeof(SMU72_Discrete_GraphicsLevel) * i)
up_hyst_offset   3193 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 				offset = up_hyst_offset & ~0x3;
up_hyst_offset   3195 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 				tmp = phm_set_field_to_u32(up_hyst_offset, tmp, levels[i].UpHyst, sizeof(uint8_t));
up_hyst_offset   3224 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 				up_hyst_offset = mclk_array + (sizeof(SMU72_Discrete_MemoryLevel) * i)
up_hyst_offset   3228 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 				offset = up_hyst_offset & ~0x3;
up_hyst_offset   3230 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 				tmp = phm_set_field_to_u32(up_hyst_offset, tmp, mclk_levels[i].UpHyst, sizeof(uint8_t));